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ADS5277 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS5277
Beschreibung 65MSPS Analog-to-Digital Converter
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 28 Seiten
ADS5277 Datasheet, Funktion
BurrĆBrown Products
from Texas Instruments
ADS5277
SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005
8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter
with Serial LVDS Interface
FEATURES
Maximum Sample Rate: 65MSPS
10-Bit Resolution
No Missing Codes
Total Power Dissipation:
Internal Reference: 911mW
External Reference: 845mW
CMOS Technology
Simultaneous Sample-and-Hold
61.7dBFS SNR at 5MHz IF
3.3V Digital/Analog Supply
Serialized LVDS Outputs
Integrated Frame and Bit Patterns
Option to Double LVDS Clock Output Currents
Four Current Modes for LVDS
Pin- and Format-Compatible Family
TQFP-80 PowerPAD™ Package
APPLICATIONS
Portable Ultrasound Systems
Tape Drives
Test Equipment
DESCRIPTION
The ADS5277 is a high-performance, CMOS,
65MSPS, 8-channel analog-to-digital converter
(ADC). Internal references are provided, simplifying
system design requirements. Low power consumption
allows for the highest of system integration densities.
Serial LVDS (low-voltage differential signaling)
outputs reduce the number of interface lines and
package size.
MODEL
ADS5270
ADS5271
ADS5272
ADS5273
RELATED PRODUCTS
RESOLUTION
(BITS)
12
12
12
12
SAMPLE RATE
(MSPS)
40
50
65
70
CHANNELS
8
8
8
8
An integrated phase lock loop (PLL) multiplies the
incoming ADC sampling clock by a factor of 12. This
high-frequency clock is used in the data serialization
and transmission process. The word output of each
internal ADC is serialized and transmitted either MSB
or LSB first. The word consists of 12 bits, of which
the 2 LSBs are zeroes and the remaining 10 bits
correspond to the output from the ADC. This
formatting is done in order to keep the interface
compatible with the 12-bit parts of the family. In
addition to the eight data outputs, a bit clock and a
word clock are also transmitted. The bit clock is at 6x
the speed of the sampling clock, whereas the word
clock is at the same speed of the sampling clock.
The ADS5277 provides internal references, or can
optionally be driven with external references. Best
performance is achieved through the internal
reference mode.
The ADS5277 is available in a PowerPAD TQFP-80
package and is specified over a –40°C to +85°C
operating range.
ADCLK
6x ADCLK
12x ADCLK
PLL
1x ADCLK
I N1 P
IN1N
S/H
I N2 P
IN2N
S/H
I N3 P
IN3N
S/H
I N4 P
IN4N
S/H
I N5 P
IN5N
S/H
I N6 P
IN6N
S/H
I N7 P
IN7N
S/H
I N8 P
IN8N
S/H
10−Bit
ADC
10−Bit
ADC
10−Bit
ADC
10−Bit
ADC
10−Bit
ADC
10−Bit
ADC
10−Bit
ADC
10−Bit
ADC
Se riali ze r
Se riali ze r
Se riali ze r
Se riali ze r
Se riali ze r
Se riali ze r
Se riali ze r
Se riali ze r
Reference
Registers
Control
I NT /E X T
LCLKP
LCLKN
ADCLKP
ADCLKN
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated






ADS5277 Datasheet, Funktion
ADS5277
SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005
www.ti.com
AC CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2k, internal voltage reference, and LVDS buffer at 3.5mA per
channel, unless otherwise noted.
PARAMETER
DYNAMIC CHARACTERISTICS
SFDR Spurious-Free Dynamic Range
HD2 2nd-Order Harmonic Distortion
HD3 3rd-Order Harmonic Distortion
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
Crosstalk
IMD3
Two-Tone, Third-Order
Intermodulation Distortion
CONDITIONS
ADS5277
MIN
TYP
MAX
UNITS
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 5MHz
5MHz Full-Scale Signal Applied to 7 Channels;
Measurement Taken on the Channel with No Input Signal
f1 = 9.5MHz at –7dBFS
f2 = 10.2MHz at –7dBFS
75
82
75
60.5
60.4
9.7
84
85
84
81
97
95
90
84
90
88
88
85
61.7
61.7
61.7
61.6
61.7
61.7
61.7
61.6
10
–89
93
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
dBc
dBFS
6

6 Page









ADS5277 pdf, datenblatt
ADS5277
SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005
www.ti.com
PIN DESCRIPTIONS
NAME
ADCLK
ADCLKN
ADCLKP
AVDD
AVSS
CS
IN1N
IN1P
IN2N
IN2P
IN3N
IN3P
IN4N
IN4P
IN5N
IN5P
IN6N
IN6P
IN7N
IN7P
IN8N
IN8P
INT/EXT
ISET
LCLKN
LCLKP
LVDD
LVSS
OUT1N
OUT1P
OUT2N
OUT2P
OUT3N
OUT3P
OUT4N
OUT4P
OUT5N
OUT5P
OUT6N
OUT6P
OUT7N
OUT7P
OUT8N
OUT8P
PD
REFB
REFT
RESET
SCLK
SDATA
VCM
PIN #
71
42
41
1, 7, 14, 47, 54, 60, 63, 70, 75
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
76
3
2
6
5
10
9
13
12
49
48
52
51
56
55
59
58
69
64
20
19
25, 35
15, 17, 18, 26, 36, 43, 44, 46
22
21
24
23
28
27
30
29
32
31
34
33
38
37
40
39
16
66
67
45
78
77
65
I/O DESCRIPTION
I Data Converter Clock Input
O Negative LVDS ADC Clock Output
O Positive LVDS ADC Clock Output
I Analog Power Supply
I Analog Ground
I Chip Select; 0 = Select, 1 = No Select
I Channel 1 Differential Analog Input Low
I Channel 1 Differential Analog Input High
I Channel 2 Differential Analog Input Low
I Channel 2 Differential Analog Input High
I Channel 3 Differential Analog Input Low
I Channel 3 Differential Analog Input High
I Channel 4 Differential Analog Input Low
I Channel 4 Differential Analog Input High
I Channel 5 Differential Analog Input Low
I Channel 5 Differential Analog Input High
I Channel 6 Differential Analog Input Low
I Channel 6 Differential Analog Input High
I Channel 7 Differential Analog Input Low
I Channel 7 Differential Analog Input High
I Channel 8 Differential Analog Input Low
I Channel 8 Differential Analog Input High
I Internal/External Reference Select; 0 = External, 1 = Internal. Weak pull-up to supply.
I/O Bias Current Setting Resistor of 56.2kto Ground
O Negative LVDS Clock
O Positive LVDS Clock
I LVDS Power Supply
I LVDS Ground
O Channel 1 Negative LVDS Data Output
O Channel 1 Positive LVDS Data Output
O Channel 2 Negative LVDS Data Output
O Channel 2 Positive LVDS Data Output
O Channel 3 Negative LVDS Data Output
O Channel 3 Positive LVDS Data Output
O Channel 4 Negative LVDS Data Output
O Channel 4 Positive LVDS Data Output
O Channel 5 Negative LVDS Data Output
O Channel 5 Positive LVDS Data Output
O Channel 6 Negative LVDS Data Output
O Channel 6 Positive LVDS Data Output
O Channel 7 Negative LVDS Data Output
O Channel 7 Positive LVDS Data Output
O Channel 8 Negative LVDS Data Output
O Channel 8 Positive LVDS Data Output
I Power-Down; 0 = Normal, 1 = Power-Down. Weak pull-down to ground.
I/O Reference Bottom Voltage (2resistor in series with a capacitor 0.1µF to ground)
I/O Reference Top Voltage (2resistor in series with a capacitor 0.1µF to ground)
I Reset to Default; 0 = Reset, 1 = Normal. Weak pull-down to ground.
I Serial Data Clock
I Serial Data input
O Common-Mode Output Voltage
12

12 Page





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