PDF ADS5242 Data sheet ( Hoja de datos )

Número de pieza	ADS5242
Descripción	65MSPS Analog-to-Digital Converter
Fabricantes	Burr-Brown Corporation
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No Preview Available ! BurrĆBrown Products from Texas Instruments ADS5242 SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES • Maximum Sample Rate: 65MSPS • 12-Bit Resolution • No Missing Codes • Total Power Dissipation Internal Reference: 660mW External Reference: 594mW • CMOS Technology • Simultaneous Sample-and-Hold • 70.8dBFS SNR at 10MHz IF • 3.3V Digital/Analog Supply • Serialized LVDS Outputs • Integrated Frame and Bit Patterns • Option to Double LVDS Clock Output Currents • Four Current Modes for LVDS • Pin- and Format-Compatible Family • HTQFP-64 PowerPAD™ Package APPLICATIONS • Portable Ultrasound Systems • Tape Drives • Test Equipment • Optical Networking • Communications DESCRIPTION The ADS5242 is a high-performance, 65MSPS, 4-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. MODEL ADS5240 RELATED PRODUCTS RESOLUTION (BITS) 12 SAMPLE RATE (MSPS) 40 CHANNELS 4 An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the four data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock. The ADS5242 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. The device is available in an HTQFP-64 PowerPAD package and is specified over a –40°C to +85°C operating range. ADCLK 6x ADCLK 12x ADCLK PLL 1x ADCLK IN1P IN1N S/H IN2P IN2N S/H IN3P IN3N S/H IN4P IN4N S/H 12− Bit ADC 12− Bit ADC 12− Bit ADC 12− Bit ADC Serializer Serializer Serializer Serializer R e fe re n c e Registers Control INT/EXT LCLKP LCLKN ADCLKP ADCLKN OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated 1 page ADS5242 www.ti.com SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 ELECTRICAL CHARACTERISTICS (continued) TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. All values are applicable after the device has been reset. PARAMETER ANALOG INPUT Differential Input Capacitance Analog Input Common-Mode Range Differential Input Voltage Range Voltage Overload Recovery Time(7) Input Bandwidth DIGITAL DATA INPUTS VIH High-Level Input Voltage VIL Low-Level Input Voltage CIN Input Capacitance DIGITAL DATA OUTPUTS Data Format Data Bit Rate SERIAL INTERFACE SCLK Serial Clock Input Frequency TEST CONDITIONS Internal Reference External Reference –3dBFS, 25Ω Series Resistances ADS5242 MIN TYP MAX UNITS 4.0 VCM ± 50 2.03 2.03 × (VREFT – VREFB) 3.0 300 pF mV VPP VPP CLK Cycles MHz 2.2 0.6 3.0 Straight Offset Binary 240 780 20 V V pF Mbps MHz (7) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value when the pulse is switched from ON (high) to OFF (low). REFERENCE SELECTION MODE Internal Reference; FSR = 2.03VPP External Reference; FSR = 2.03 × (VREFT – VREFB) INT/EXT 1 0 DESCRIPTION Default with internal pull-up. Internal reference is powered down. The common-mode voltage of the external reference should be within 50mV of VCM. VCM is derived from the internal bandgap voltage. 5 5 Page www.ti.com Top View ADS5242 SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005 PIN CONFIGURATION HTQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD 1 IN1P 2 IN1N 3 AVSS 4 AVDD 5 AVSS 6 IN2P 7 IN2N 8 AVSS 9 AVDD 10 LVSS 11 PD 12 LVSS 13 LVSS 14 LCLKP 15 LCLKN 16 ADS5242 48 AVDD 47 IN4N 46 IN4P 45 AVSS 44 AVDD 43 AVSS 42 IN3N 41 IN3P 40 AVSS 39 AVDD 38 LVSS 37 RESET 36 LVSS 35 LVSS 34 ADCLKN 33 ADCLKP 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 11 Page

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