PDF AS7C33128FT36B Data sheet ( Hoja de datos )

Número de pieza	AS7C33128FT36B
Descripción	(AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
Fabricantes	Alliance Semiconductor Corporation
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February 2005 AS7C33128FT32B AS7C33128FT36B ® 3.3V 128K × 32/36 Flow Through Synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bits • Fast clock to data access: 6.5/7.5/8.0/10.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous flow through operation • Asynchronous output enable control • Available in 100-pin TQFP package • Individual byte write and Global write www.DataSheet4U.com • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Linear or interleaved burst control • Snooze mode for reduced power standby • Common data inputs and data outputs Logic block diagram CLK ADV ADSC ADSP A[18:0] GWE BWE BWd BWc BWb BWa CE0 CE1 CE2 ZZ OE LBO CLK CE Q0 Burst logic CLR Q1 128K × 32/36 19 D Q 19 17 19 Memory array CE Address register CLK D DQd Q Byte write registers CLK D DQc Q Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK 36/32 36/32 4 Power down DQ Enable CE register CLK D Enable Q delay register CLK OE Output buffer Input registers CLK 36/32 DQ[a:d] Selection guide –65 -75 -80 -10 Units Minimum cycle time 7.5 8.5 10 12 ns Maximum clock access time 6.5 7.5 8.0 10.0 ns Maximum operating current 275 250 215 185 mA Maximum standby current 90 85 75 75 mA Maximum CMOS standby current (DC) 30 30 30 30 mA 2/8/05; v.1.2 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C33128FT32B AS7C33128FT36B ® Signal descriptions Pin CLK A,A0,A1 DQ[a,b,c,d] CE0 www.DataSheet4CUE.c1o, mCE2 ADSP ADSC ADV GWE BWE BW[a,b,c,d] OE LBO ZZ NC I/O Properties Description I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. I/O SYNC Data. Driven as output when the chip is enabled and when OE is active. I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information. I SYNC Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode. I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode. I SYNC Advance. Asserted low to continue burst read/write. I SYNC Global write enable. Asserted low to write all 32/36 bits. When high, BWE and BW[a:d] control write enable. I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs. Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of I SYNC BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive, the cycle is a read cycle. I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode. I STATIC Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. - - No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 2/8/05; v.1.2 Alliance Semiconductor P. 5 of 19 5 Page AS7C33128FT32B AS7C33128FT36B ® Key to switching waveforms Rising input Falling input don’t care Timing waveform of read cycle www.DataSheet4U.com CLK tCYC tCH tCL tADSPS ADSP ADSC tADSPH tADSCS tADSCH tAS tAH Address A1 A2 GWE, BWE tWS tWH tCSS CE0, CE2 tCSH LOAD NEW ADDRESS A3 CE1 ADV OE tADVS tADVH ADV inserts wait states Undefined Dout tOE tLZOE tHZOE tOH Q(A1) Q(A2Ý01) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) tCD tHZC Read Q(A1) Suspend Read Q(A1) Read Burst ReadBurst Read Suspend Burst Read Read Burst Read Burst Read Burst Read Q(A2) Q(A 2Ý01) Q(A 2Ý10) Read Q(A 2Ý11) Q(A3) Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11) DSEL Q(A 2Ý10) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care. 2/8/05; v.1.2 Alliance Semiconductor P. 11 of 19 11 Page

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