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PC28F320 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer PC28F320
Beschreibung Intel StrataFlash Memory
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
PC28F320 Datasheet, Funktion
www.DataSheet4U.com
Intel StrataFlash® Memory (J3)
256-Mbit (x8/x16)
Product Features
Datasheet
Performance
Architecture
— 110/115/120/150 ns Initial Access Speed — Multi-Level Cell Technology: High
— 125 ns Initial Access Speed (256 Mbit
density only)
— 25 ns Asynchronous Page mode Reads
— 30 ns Asynchronous Page mode Reads
(256Mbit density only)
— 32-Byte Write Buffer
—6.8 µs per byte effective
programming time
Software
Density at Low Cost
— High-Density Symmetrical 128-Kbyte
Blocks
—256 Mbit (256 Blocks) (0.18µm only)
—128 Mbit (128 Blocks)
64 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
Quality and Reliability
— Operating Temperature:
-40 °C to +85 °C
— Program and Erase suspend support
— 100K Minimum Erase Cycles per Block
— Flash Data Integrator (FDI), Common
Flash Interface (CFI) Compatible
Security
— 128-bit Protection Register
—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
— Absolute Protection with VPEN = GND
— Individual Block Locking
— Block Erase/Program Lockout during
Power Transitions
— 0.18 µm ETOX™ VII Process (J3C)
— 0.25 µm ETOX™ VI Process (J3A)
Packaging and Voltage
— 56-Lead TSOP Package
— 64-Ball Intel® Easy BGA Package
— Lead-free packages available
— 48-Ball Intel® VF BGA Package (32 and
64 Mbit) (x16 only)
— VCC = 2.7 V to 3.6 V
— VCCQ = 2.7 V to 3.6 V
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3)
device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-
Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-
per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed
interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future
devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash®
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel®
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Order Number: 290667-021
March 2005






PC28F320 Datasheet, Funktion
Contents
www.DataSheet4U.com
Date of
Revision
07/27/01
10/31/01
03/21/02
Version
-009
-010
-011
Description
Added Figure 4, 3 Volt Intel StrataFlash® Memory VF BGA Package (32 Mbit)
Added Figure 5, 3 Volt Intel StrataFlash® Memory VF BGA Mechanical
Specifications
Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns
Added parameter values for –40 °C operation to Lock-Bit and Suspend Latency
Updated VLKO and VPENLK to 2.2 V
Removed Note #4, Section 6.4 and Section 6.6
Minor text edits
Added notes under lead descriptions for VF BGA Package
Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
Removed byte mode read current row un DC characteristics
Added ordering information for VF BGA Package
Minor text edits
Changed datasheet to reflect the best known methods
Updated max value for Clear Block Lock-Bits time
Minor text edits
12/12/02
01/24/03
12/09/03
1/3/04
1/23/04
1/23/04
5/19/04
7/7/04
11/23/04
3/24/05
-012
-013
-014
-015
-016
-016
-018
-019
-020
-021
Added nomenclature for J3C (0.18 µm) devices.
Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128
Mb J3C device. Added “TE” package designator for J3C TSOP package.
Revised Asynchronous Page Read description. Revised Write-to-Buffer flow
chart. Updated timing waveforms. Added 256-Mbit J3C pinout.
Added 256Mbit device timings, device ID, and CFI information. Also corrected
VLKO specification.
Corrected memory block count from 257 to 255.
Memory block count fix.
Restructured the datasheet layout.
Added lead-free part numbers and 8-word page information.
Added Note to DC Voltage Characteristics table; “Speed Bin” to Read Operations
table; Corrected format for AC Waveform for Reset Operation figure; Corrected
“R” and “8W” headings in Enhanced Configuration Register table because they
were transposed; Added 802 and 803 to ordering information and corrected 56-
Lead TSOP combination number.
Corrected ordering information.
6 Datasheet

6 Page









PC28F320 pdf, datenblatt
256-Mbit J3 (x8/x16)
3.2 Easy BGA (J3) Package
Figure 4. Intel StrataFlash® Memory (J3) Easy BGA Mechanical Specifications
Ball A1
Corner
D
Ball A1
Corner
S1
www.DataSheet4U.com
E
12 3 4 5 6 7
A
B
C
D
E
F
G
H
Top View - Ball side down
8
8 7 6 5 4 3 21
A
B
C
D
E
F
G
H
Bottom View - Ball Side Up
S2
b
e
A1
A2
A Seating
Plane
Y
Note: Drawing not to scale
Table 2. Easy BGA Package Dimensions
Millimeters
Inches
Symbol Min
Package Height
A
Ball Height
A1
Package Body Thickness
A2
Ball (Lead) Width
b
Package Body Width (32 Mb, 64 Mb, 128 Mb, 256 Mb) D
Package Body Length (32 Mb, 64 Mb, 128 Mb)
E
Package Body Length (256 Mb)
E
Pitch
[e]
Ball (Lead) Count
N
Seating Plane Coplanarity
Y
Corner to Ball A1 Distance Along D (32/64/128/256 Mb) S1
Corner to Ball A1 Distance Along E (32/64/128 Mb)
S2
Corner to Ball A1 Distance Along E (256 Mb)
S2
0.250
0.330
9.900
12.900
14.900
1.400
2.900
3.900
Nom
0.780
0.430
10.000
13.000
15.000
1.000
64
1.500
3.000
4.000
Max
1.200
0.530
10.100
13.100
15.100
0.100
1.600
3.100
4.100
Notes Min
0.0098
0.0130
1 0.3898
1 0.5079
1 0.5866
1 0.0551
1 0.1142
1 0.1535
Nom
0.0307
0.0169
0.3937
0.5118
0.5906
0.0394
64
0.0591
0.1181
0.1575
Max
0.0472
0.0209
0.3976
0.5157
0.5945
0.0039
0.0630
0.1220
0.1614
NOTES:
1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at;
www.intel.com/design/packtech/index.htm
2. For Packaging Shipping Media information see www.intel.com/design/packtech/index.htm
12 Datasheet

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