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PDF DSD1702 Data sheet ( Hoja de datos )
| Número de pieza | DSD1702 | |
| Descripción | AUDIO DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
ENHANCED MULTIFORMAT, DELTA-SIGMA,
AUDIO DIGITAL-TO-ANALOG CONVERTER
FEATURES
D Supports DSD and PCM Format
D Accepts 16-, 18-, 20- and 24-Bit Audio Data for
PCM Format
www.DataSheet4UD.comAccepts Direct Stream Digital (1 bit)
D Analog Performance (VCC = 5 V):
– Dynamic Range: 106 dB Typ
– SNR: 106 dB Typ
– THD+N: 0.0015% Typ
– Full–Scale Output: 3.1 V(pp) Typ
D Includes 8x Oversampling Digital Filter for
PCM Format:
– Stopband Attenuation: –60 dB
– Passband Ripple: ±0.02 dB
D Including Digital DSD Filter For DSD Format:
– Passband Choices: 50 kHz, 70 kHz or
60 kHz at –3 dB
D Sampling Frequency:
– PCM Mode: 10 kHz to 200 kHz
– DSD Mode: 64 × 44.1 kHz
D System Clock:
– 128fs 192fs, 256fs, 384fs 512fs, 768fs
D Data Formats:
– Standard, I2S, and Left-Justified for PCM
Direct Stream Digital
D User-Programmable Mode Controls:
– Digital Attenuation
– Digital De-Emphasis
– Digital Filter Roll-Off: Sharp or Slow Soft
Mute
– Zero Detect Mute
– Zero Flags for Each Output
D Dual Supply Operation:
5-V Analog, 3.3-V Digital
D 5-V Tolerant Digital Inputs
D Small 20-Lead QSOP Package
APPLICATIONS
D Universal A/V Players
D SACD Players
D Car Audio Systems
D Other Applications Requiring 24-Bit Audio
DESCRIPTION
The DSD1702 is a CMOS, monolithic, stereo
digital-to-analog converter that supports both PCM
audio data format and direct stream digital (DSD) audio
data format.
The device includes an 8x digital interpolation filter for
PCM signals. A digital DSD filter provides three different
selectable frequency response options, followed by
Burr-Brown’s enhanced multilevel delta-sigma
modulator employing 4th-order noise shaping and
8-level amplitude quantization. This design achieves
excellent dynamic performance and improved
tolerance to clock jitter.
DSD1702 sampling rates of up to 192 kHz for PCM
mode and 44.1 kHz × 64 for DSD mode are supported.
A full set of user-programmable functions is accessible
through a 3-wire serial control port, supporting register
write functions.
The DSD1702 is available in a 20-lead QSOP package.
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precaustions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
www.ti.com
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
electrical characteristics, TA = 25°C, VDD = 3.3 V, VCC = 5 V (unless otherwise noted) (continued)
In PCM mode, fs = 44.1 kHz, system clock = 256fs, 24-bit data
In DSD mode, fs = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data
PARAMETERS
Dynamic Performance(7)
TEST CONDITIONS
DSD1702E
MIN TYP
UNITS
MAX
PCM MODE
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THD+N at VOUT = 0 dB
Dynamic range
Signal-to-noise ratio(8)
Channel separation
Level linearity error
DSD MODE (at fs = 64 × 44.1 kHz)
THD+N
Dynamic range
fs = 44.1 kHz
fs = 96 kHz
fs = 192 kHz
EIAJ, A-Weighted,
A-Weighted,
fs = 192 kHz
EIAJ, A-Weighted,
A-Weighted,
fs = 192 kHz
fs = 44.1 kHz
fs = 96 kHz
fs = 192 kHz
VOUT = –90 dB
VOUT = 0 dB, EIAJ
EIAJ, A-Weighted
fs = 44.1 kHz
fs = 96 kHz
fs = 44.1 kHz
fs = 96 kHz
0.0015% 0.002%
0.0020%
0.0025%
103 106
106
105
103 106
106
105
100 103
103
102
±0.5
dB
dB
dB
dB
0.0015%
106
dB
Signal–to–noise ratio
EIAJ, A-Weighted
106 dB
Channel separation
103 dB
Level linearity error
DC Accuracy
VOUT = –90 dB
±0.5 dB
Gain error
±1.0 ±6.0 %/FSR
Gain mismatch, channel-to-channel
±1.0 ±3.0 %/FSR
Bipolar zero error
Analog Output
VOUT = 0.5 VCC at BPZ
±30 ±60 mV
Output voltage
Center voltage
Load impedance
Full scale (–0dB)
AC load
62%/VCC
50%/VCC
5
V(PP)
VDC
kΩ
Digital Filter Performance
8x Interpolation Filter
Sharp roll off Filter
Passband
Passband
Stopband
Passband ripple
±0.02 dB
–3 dB
0.546fs
0.454fs
0.487fs
± 0.02 dB
Stopband Attenuation
Stopband = 0.546fs
– 60
NOTES: 7. Analog performance specs are measured by audio precision system 2 under averaging mode.
8. SNR is tested at infinite zero detection OFF.
dB
www.ti.com
5
5 Page 
DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
register write operation
All write operations for the serial control port use 16-bit data words. Figure 7 shows the control data word format.
The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (or
address). The least significant eight bits, D[7:0], contain the data to be written to the register specified by
IDX[6:0].
Figure 8 shows the functional timing diagram for the serial control port. MS is held at a logic 1 state until a register
needs to be written. To start the register write cycle, MS is set to logic 0. Sixteen clocks are then provided on
MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has completed,
the data is latched into the indexed mode control register. To write the next data, MS must be set to 1 once.
control interface timing requirements
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Figure 9 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
MSB
LSB
0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0
Register Index (or Address)
Register Data
Figure 7. Control Data Word Format MD
MS
MC
MD X 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 IDX6
Figure 8. Register Write Operation
www.ti.com
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet DSD1702.PDF ] | |
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