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R8A66597BG Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R8A66597BG
Beschreibung ASSP
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 30 Seiten
R8A66597BG Datasheet, Funktion
R8A66597FP/DFP/BG
ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
REJ03F0229-0101
Rev1.01
Oct 17, 2008
1 Overview
1.1 Overview
The R8A66597 is a Universal Serial Bus (USB) Controller equipped with USB Host functions and Peripheral functions
applicable for On-The-Go. When selecting the Host Controller function, it has two USB ports available for Hi-Speed,
Full-Speed, and Low-Speed transfer compliant with USB Specification Revision 2.0. When selecting the Peripheral
www.DataSheet4U.cCoomntroller function, it has one USB port available for Hi-Speed and Full-Speed transfer compliant with USB Specification
Revision 2.0.
This controller has a built-in USB transceiver and is compatible with all the transfer types defined in USB Specification
Revision 2.0.
The internal buffer memory is 8.5K, and a maximum ten pipes can be used for transferring data. For Pipe1 to Pipe9, any
endpoint address can be assigned matching the peripheral functions for communication or user system. Separate bus or
multiplex bus can be selected for the CPU connection. A split bus interface (exclusively for the DMA interface) that is
different from the CPU bus interface is provided and is suitable for systems demanding high-performance data transfer.
1.2 Features
1.2.1 Built-in Host Controller and Peripheral Controller compatible with Hi-Speed USB
Built-in USB Host Controller and Peripheral Controller
Toggle between USB Host functions and Peripheral functions is possible according to what is written to the register
Built-in USB transceiver
1.2.2 Low power consumption
1.5V core power consumes less power when operating
With the installed Low Power Sleep Mode functions, less power is consumed when the USB is not in use, which is
also applicable for portable devices
Standby power consumption can be greatly reduced by keeping only the VIF power source ON when not using the
USB function.
Operational with a 3.3V single power supply using the internal 1.5V core power regulator
1.2.3 Space-saving package
Few external devices and space-saving package
VBUS signal can be connected directly to the controller input pin
Built-in D+ pull-up resistor (for Peripheral function)
Built-in D+ and D- pull-down resistors (for Host function)
Built-in D+ and D- terminating resistors (for Hi-Speed operations)
Built-in D+ and D- output resistors (for Full-Speed and Low-Speed operations)
Rev1.01 Oct 17, 2008
page 1 of 183






R8A66597BG Datasheet, Funktion
R8A66597FP/DFP/BG
1.4 Pin Description
Pin descriptions are given in Table 1.1, and the processing method of unused pins is given in Table 1.2.
Table 1.1 Pin Description
Pin Name
Name
I/O
Function
Pin Status *5)
Number
of Pins Being
Reset
www.DataSheet4U.com
D15-0
AD7-1
Data bus
Multiplex
address bus
I/O This is a 16-bit data bus.
When selecting to the multiplex bus, these pins
I/O are used in the time division as a part of the
data bus (D7-D1) or address bus (A7-A1).
A7-1
Address bus
IN
This is the address bus.
A0 does not exist for the 16-bit data bus.
ALE
Address latch
enabled
IN
While selecting to the multiplex bus, the A7 pin
is used as an ALE signal.
CPU bus
interface
CS_N
RD_N
Chip select
Read strobe
IN The controller is selected in "L" level.
IN
Reads the data from the register of this
controller in "L" level.
WR0_N
D7-0 Byte write
strobe
IN
Writes D7-D0 in the register of this controller at
the rising edge.
WR1_N
D15-8 byte write
strobe
IN
Writes D15-D8 in the register
at the rising edge.
of this controller
MPBUS
Bus mode
selection
This is a separate bus in "L" level. This is a
IN multiplex bus in "H" Level. Fix either "H" or "L"
level.
SPLIT bus SD7-0
interface
Split data bus
I/O
When the split bus is selected, it functions as
the split data bus.
DREQ0_N
DREQ1_N
DMA request
OUT
Notifies the DMA
port and D1FIFO
transfer
port.
request
of
D0FIFO
DMA bus
DACK0_N
DACK1_N
DMA
acknowledgeme
nt
IN
Enter the DMA acknowledgement signal of
D0FIFO port and D1FIFO port.
interface
For FIFO port access write direction: Receives
DEND0_N
DEND1_N
DMA transfer
end
transmission completion signal as an input
I/O signal from other chips or CPU.
For FIFO port access read direction: Shows
the last transmitted data as an output signal.
Interrupt/
Notifies various types of interrupts related to
SOF output
USB communication by "L" active. Active is by
INT_N
Interrupt OUT default "L" active, however it can be changed
to "H" active by modifying the setup value of
INTA bit in the software.
For Host function:
When the controller issues an SOF, outputs an
SOF_N
SOF pluse
output
OUT
SOF pulse by "L" active.
For Peripheral function:
When an SOF is detected, outputs an SOF
pulse by "L" active.
Clock
XIN
XOUT
Input for
oscillation
Output for
oscillation
IN
Connect crystal oscillator between XIN and
XOUT. Connect external clock signal to XIN in
OUT
order to
XOUT.
input
external
clock,
and
leave
open
System
control
USB bus
interface
Reset signal
IN Resets this controller at "L" level.
16
7
1
1
1
1
1
8
2
2
2
1
1
1
1
1
*2) *2)
Input Input
*3) *3)
Input Input
Input
*4)
Input
Input
*4)
Input
Input
*4)
Input
*4)
Input
*4)
Input
*4)
Input Input
*1) *1)
Input Input
(Hi-Z) (Hi-Z)
HH
Input Input
Input Input
(Hi-Z) (Hi-Z)
HH
HH
Input Input
(L) (H)
Rev1.01 Oct 17, 2008 Page 6 of 183
Confidential

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R8A66597BG pdf, datenblatt
R8A66597FP/DFP/BG
1.6.7 Importing the external devices
This controller is equipped with the external devices listed below. Also, as the VBUS pin has 5V-tolerant, the user
system can connect the VBUS signal directly to this controller.
(1) Resistors necessary in D+ and D-line control
The following D+ and D- resistors necessary for USB communication are installed:
D+ pull-up resistor (for Peripheral operations)
D+ pull-down resistor (for host operations)
D+ and D- termination resistors (for Hi-Speed operations)
D+ and D- output resistors (for Full-Speed and Low-Speed operations)
(2) 48MHz and 480MHz PLL
Operations can be executed by selecting one of the three types of external clocks (12MHz/24MHz/48MHz).
www.DataSheet4U.co(m3) 3.3V 1.5V regulator
1.5V core power is generated in this controller. In the system where a 3.3V interface power is used, this controller
can be operated on a single power supply.
Rev1.01 Oct 17, 2008 Page 12 of 183
Confidential

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