Datenblatt-pdf.com


R8A66171SP Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R8A66171SP
Beschreibung A2RT
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 23 Seiten
R8A66171SP Datasheet, Funktion
R8A66171DD/SP
A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)
REJ03F0269-0100
Rev. 1.00
Feb.19.2008
DESCRIPTION
The R8A66171 is an integrated circuit for asynchronous serial data communications. It is used in combina-
tion with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is
the succession product of M66230.
FEATURES
Baud rate generator
4-byte FIFO data buffer for transmission and reception
www.DataSheet4UE.crormor detection : CRC-CCITT
Wakeup function
Majority-voting system by sampling three points of received data
Transmission / reception data format ( number of bits )
Start bit 1
Data bit 8
Wakeup bit 1 or nil
Parity bit 1 or nil
Stop bit 1 or 2
Transmission speed
500Kbps (max)
Access time
ta (/RD-D) : 100ns
High output current
IOH=-24mA IOL=24mA TxD, /RTS, P0, P1 pins
Schmitt triggered input RxD, /CTS, /RESET pins
Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V)
Wide operating temperature range (Ta=-40~85OC)
APPLICATION
Data communication control that uses microprocessor
PIN CONFIGURATION (TOP VIEW)
D0
D1
DATA BUS
D2
D3
D4
D5
D6
D7
READ CONTROL INPUT RD
WRITE CONTROL INPUT WR
COMMAND/DATA C/D
CONTROL INPUT GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 TxD TRANSMISSION DATA OUTPUT
22 RxD RECEPTION DATA INPUT
21 CTS CLEAR-TO-SEND INPUT
20 RTS REQUEST-TO-SEND OUTPUT
19 P0
PORT OUTPUT
18 P1
17 INT INTERRUPT OUTPUT
16 CS CHIP SELECT INPUT
15 RESET RESET INPUT
14 X1 CLOCK INPUT
13 X2 CLOCK OUTPUT
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 1 of 22






R8A66171SP Datasheet, Funktion
R8A66171DD/SP
Example : Block length=6
MCU
DATA DATA DATA DATA
Transmit data buffer(FIFO)
Transmit buffer(P S)
or
TxD pin
DATA DATA
Transmit data buffer(FIFO)
Receive data buffer (FIFO)
www.DataSheet4U.com The receive data buffer (FIFO) consists of 4-bytes. The receive data buffer (FIFO) functions according
to the block length.
Block length=1~3
When the data of the block length is received and /INT is set to low-level, the interrupt output /INT
becomes low-level. The MCU acknowledges the packet end by setting the D0 bit of the status1
information.
In this case, the MCU should read all data from the receive data buffer (FIFO).
At the packet end, the data from the receive buffer cannot be transmitted to the receive data buffer
(FIFO) until the MCU reads all data in the receive data buffer (FIFO). The MCU cannot read data in
the receive data buffer until the packet end.
Example : Block length=2
MCU
DATA DATA
Receive data buffer(FIFO)
(Interrupt-packet end)
Receive buffer(P S)
RxD pin
Block length=4 or more
When 4-byte data enters the receive data buffer (FIFO) (buffer full) and /INT is set to low-active, the
interrupt output /INT becomes low-level. The MCU acknowledges the buffer full status by setting the
D1 bit of the status1 information.
In this case, the MCU should read all data in the receive data buffer (FIFO).
When the last data enters the receive data buffer (FIFO), the packet end becomes the same operation
as for 1~3 byte block length. If the block length is a multiple of four, the D0 and D1 bits of the status1
information are set when the last data enters the receive data buffer (FIFO). At packet end or buffer
full, the new data cannot be transferred from the receive buffer to the receive data buffer (FIFO). The
MCU cannot read data in the receive data buffer (FIFO) until packet end or buffer full occurs.
Example : Block length=6
MCU
DATA DATA DATA DATA
Receive data buffer(FIFO)
(First interrupt-buffer full)
or
Receive buffer(P S)
RxD pin
DATA DATA
Receive data buffer(FIFO)
(Second interrupt-packet end)
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 6 of 22

6 Page









R8A66171SP pdf, datenblatt
R8A66171DD/SP
STATUS INFORMATION
Status 1 and 2 cannot address setting from external pin. Discrimination of status used to D7 bit.
Status 1 and 2 has read mutually. (There are not continuity read of same status.)
Status1
1 indicates that a CRC error is found in the
received data
1 indicates that a parity error is found in the
received data
www.DataSheet4U.com
1 indicates that an overrun error is found in the
received data
1 indicates that a framing error is found in the
received data
1 indicates that the transmission
data buffer (FIFO) is empty
1 indicates that the received data
buffer (FIFO) is full
1 indicates that the received data
buffer (FIFO) is packet end
0
CRCE
PE
OE
FE TxBEMP RxBFULL RxBPE
D7 D6 D5 D4 D3 D2 D1 D0
Status2
1 indicates that the transmission*
characters are not found in the
transmitter
1 indicates that packet transmission*
is complete from the transmitter
1 indicates that wakeup is maintained
1 indicates the wakeup mode
1L
L
L
TxEMP
TxPE
WUEN WUMODE
D7 D6 D5 D4 D3 D2 D1 D0
* Transmitter = Transmit data buffer (FIFO) + Transmit buffer
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 12 of 22

12 Page





SeitenGesamt 23 Seiten
PDF Download[ R8A66171SP Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
R8A66171SPA2RTRenesas Technology
Renesas Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche