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PDF R8A66162SP Data sheet ( Hoja de datos )
| Número de pieza | R8A66162SP | |
| Descripción | 32-BIT LED DRIVER | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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R8A66162SP
32-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH
REJ03F0263-0100
Rev. 1.00
Jan. 24. 2008
DESCRIPTION
The R8A66162SP is a semiconductor integrated circuit for LED array driver with 32-bit serial-input, parallel -
output shift register, equipped with direct set input and output latches.
The R8A66162SP guarantees sufficient 24mA (Vcc=5.0V case) output current to drive anode common LED,
allowing 32-bit simultaneous and continuous current output. The parallel outputs are open-drain outputs.
In addition, as this product has been designed in complete CMOS, power consumption can be greatly
reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures
the realization of an easy printed circuit. R8A66162SP is the succession product of M66313FP.
www.DataSheetF4UE.coAmTURES
● Anode common LED drive
● VCC 5V or 3.3V single power supply
● High output current: All parallel outputs Q1~Q32 IOL=24mA (at VCC=5.0V), IOL=12mA (at VCC=3.3V),
LEDs can be turned on simultaneously.
● Low power dissipation: 200uW/package (max) (VCC=5.0V, Ta=25OC, quiescent state)
● High noise margin: Employment of Schmitt-trigger circuit on all inputs allows application with long wiring.
● Direct set input (SD)
● Open-drain output (Q1~Q32)
● Serial data output for cascading (SQ32)
● Wide operating temperature range (Ta=-40oC~+85oC)
● Pin configuration for easy layout on PCB. (Pin configuration allows easy cascade connection or LED
connection)
APPLICATION
● LED array drive, The various LED display modules
● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipments
BLOCK DIAGRAM
LOGIC DIAGRAM
PARALLEL DATA OUTPUTS
Q1 Q2 Q3 Q4
234 5
SERIAL DATA
OUTPUT
Q29 Q30 Q31 Q32 SQ32
20 21 22 23 17
Vcc
9 15 37
0
LE
DS
0
LE
DS
0
LE
DS
0
LE
DS
1
CK
DS
1
CK
DS
1
CK
DS
1
CK
DS
0
LE
DS
0
LE
DS
0
LE
DS
0
LE
DS
1
CK
DS
1
CK
DS
1
CK
DS
1
CK
DS
11 10
OE A
DATA
SIGNAL
OUTPUT SERIAL OE
ENABLE DATA SIGNAL
INPUT INPUT
PARALLEL
DATA
OUTPUTS
Q1 Q32
OUTPUT FORMAT
SERIAL
DATA
OUTPUT
SQ32
1 8 16 24
14 13 12
30 36 43
CK SD LE GND
SHIFT DIRECT LATCH
CLOCK SET ENABLE
INPUT INPUT INPUT
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 1 of 7
1 page  
R8A66162SP
SWITCHING CHARACTERISTICS (Ta=-40~85 oC, Vcc=5.0V or 3.3V, unless otherwise noted)
Symbol
Parameter
fmax
tPZL
tPLZ
tPLH
tPHL
tPZL
www.DataSheet4U.tcPoLmH
tPZL
tPLZ
tPZL
tPLZ
CI
CO
Maximum clock frequency
Output “Z-L” and “L-Z” CK-Q1~Q32
propagation time
(Turned on)
CK-Q1~Q32
(Turned off)
Output “L-H” and “H-L” CK-SQ32
propagation time
Output “Z-L”
propagation time
SD-Q1~Q32
(Turned on)
Output “L-H”
propagation time
SD-SQ32
Output “Z-L” and “L-Z” LE-Q1~Q32
propagation time
(Turned on)
LE-Q1~Q32
(Turned off)
Output “Z-L” and “L-Z” OE-Q1~Q32
propagation time
(Turned on)
OE-Q1~Q32
(Turned off)
Input capacitance
Output capacitance
Test
conditions
5.0V specification
Min. Typ. Max.
4
200
3.3V specification
Min. Typ. Max.
3.3
220
Unit
MHz
ns
250 270 ns
CL=50pF
RL=1kΩ
(Note3)
125 150 ns
125 150 ns
200 220 ns
125 150 ns
125 150 ns
200 220 ns
125 150 ns
200 220 ns
OE=Vcc
10 10 pF
15 15 pF
TIMING REQUIREMENTS (Ta=-40~85 oC, Vcc=5.0V or 3.3V, unless otherwise noted)
Symbol
Parameter
tw CK, LE, SD pulse width
tsu Setup time A to CK
th Hold time A to CK
Hold time LE to CK
trec Recovery time CK to SD
Test
conditions
(Note3)
5.0V specification
Min. Typ. Max.
125
125
15
70
70
3.3V specification
Min. Typ. Max.
150
150
20
80
80
Unit
ns
ns
ns
ns
ns
Note3. Test circuit
INPUT VCC
DUT
PG
50 GND
SQ32
CL
VCC
RL
CL
Q1 Q32
(1) The pulse generator(PG) has the following characteristics(10%~90%):tr=6ns,tf=6ns
(2) The capacitance CL includes stray wiring capacitance and the probe input capacitance.
REJ03F0263-0100 Rev.1.00 Jan.24.2008
page 5 of 7
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet R8A66162SP.PDF ] | |
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