Datenblatt-pdf.com


C8051F047 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F047
Beschreibung (C8051F040 - C8051F047) 100-Pin Mixed-Signal MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 70 Seiten
C8051F047 Datasheet, Funktion
C8051F040/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 10 or 12-Bit SAR ADC
12-bit (C8051F040/1) or
10-bit (C8051F042/3/4/5/6/7) resolution
± 1 LSB INL, guaranteed no missing codes
Programmable throughput up to 100 ksps
13 External Inputs; single-ended or differential
SW programmable high voltage difference amplifier
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor
- 8-bit SAR ADC (C8051F040/1/2/3 only)
Programmable throughput up to 500 ksps
8 External Inputs, single-ended or differential
www.DataSheet4U.com Programmable amplifier gain: 4, 2, 1, 0.5
- Two 12-bit DACs (C8051F040/1/2/3 only)
Can synchronize outputs to timers for jitter-free wave-
form generation
- Three Analog Comparators
Programmable hysteresis/response time
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full- speed, non-
intrusive in-circuit/in-system debugging
- Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- IEEE1149.1 compliant boundary scan
- Complete development kit
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- 20 vectored interrupt sources
Memory
- 4352 bytes internal data RAM (4 k + 256)
- 64 kB (C8051F040/1/2/3/4/5)
or 32 kB (C8051F046/7) Flash; in-system program-
mable in 512-byte sectors
- External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
Digital Peripherals
- 8 byte-wide port I/O (C8051F040/2/4/6); 5 V tolerant
- 4 byte-wide port I/O (C8051F041/3/5/7); 5 V tolerant
- Bosch Controller Area Network (CAN 2.0B), hard-
ware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
- Programmable 16-bit counter/timer array with
6 capture/compare modules
- 5 general purpose 16-bit counter/timers
- Dedicated watch-dog timer; bi-directional reset pin
Clock Sources
- Internal calibrated programmable oscillator: 3 to
24.5 MHz
- External oscillator: crystal, RC, C, or clock
- Real-time clock mode using Timer 2, 3, 4, or PCA
Supply Voltage: 2.7 to 3.6 V
- Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
- Temperature Range: –40 to +85 °C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
VREF
12/10-bit
100 ksps
ADC
8-bit
PGA 500 ksps
ADC
HV
DIFF
AMP
12-Bit
DAC
12-Bit
DAC
C8051F041/2/3
ONLY
+ ++
- --
VOLTAGE COMPARATORS
DIGITAL I/O
CAN
2.0B
UART0
Port 0
Port 1
UART1
SMBus
SPI Bus
Port 2
Port 3
PCA
Timer 0
Port 4
Timer 1
Timer 2
Timer 3
Timer 4
Port 5
Port 6
Port 7
64 pin 100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25 MIPS)
20
INTERRUPTS
64 kB/32 kB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
JTAG
CLOCK
SANITY
CIRCUIT CONTROL
Rev. 1.4 11/04
Copyright © 2004 by Silicon Laboratories
C8051F04x






C8051F047 Datasheet, Funktion
C8051F040/1/2/3/4/5/6/7
18.1.2.Example Timing Calculation for 1 Mbit/Sec Communication ................. 231
18.2.CAN Registers................................................................................................ 233
18.2.1.CAN Controller Protocol Registers......................................................... 233
18.2.2.Message Object Interface Registers ...................................................... 233
18.2.3.Message Handler Registers................................................................... 234
18.2.4.CIP-51 MCU Special Function Registers ............................................... 234
18.2.5.Using CAN0ADR, CAN0DATH, and CANDATL to
Access CAN Registers .......................................................................... 234
18.2.6.CAN0ADR Autoincrement Feature ........................................................ 234
19. System Management BUS / I2C BUS (SMBUS0)................................................ 241
www.DataSheet4U.com 19.1.Supporting Documents ................................................................................... 242
19.2.SMBus Protocol.............................................................................................. 243
19.2.1.Arbitration............................................................................................... 243
19.2.2.Clock Low Extension.............................................................................. 244
19.2.3.SCL Low Timeout................................................................................... 244
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 244
19.3.SMBus Transfer Modes.................................................................................. 244
19.3.1.Master Transmitter Mode ....................................................................... 244
19.3.2.Master Receiver Mode ........................................................................... 245
19.3.3.Slave Transmitter Mode ......................................................................... 245
19.3.4.Slave Receiver Mode ............................................................................. 246
19.4.SMBus Special Function Registers ................................................................ 247
19.4.1.Control Register ..................................................................................... 247
19.4.2.Clock Rate Register ............................................................................... 250
19.4.3.Data Register ......................................................................................... 251
19.4.4.Address Register.................................................................................... 251
19.4.5.Status Register....................................................................................... 252
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 257
20.1.Signal Descriptions......................................................................................... 258
20.1.1.Master Out, Slave In (MOSI).................................................................. 258
20.1.2.Master In, Slave Out (MISO).................................................................. 258
20.1.3.Serial Clock (SCK) ................................................................................. 258
20.1.4.Slave Select (NSS) ................................................................................ 258
20.2.SPI0 Master Mode Operation ......................................................................... 259
20.3.SPI0 Slave Mode Operation ........................................................................... 261
20.4.SPI0 Interrupt Sources ................................................................................... 261
20.5.Serial Clock Timing......................................................................................... 262
20.6.SPI Special Function Registers ...................................................................... 263
21. UART0.................................................................................................................... 267
21.1.UART0 Operational Modes ............................................................................ 268
21.1.1.Mode 0: Synchronous Mode .................................................................. 268
21.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 269
21.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 271
21.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 272
21.2.Multiprocessor Communications .................................................................... 272
6 Rev. 1.4

6 Page









C8051F047 pdf, datenblatt
C8051F040/1/2/3/4/5/6/7
22. UART1
Figure 22.1. UART1 Block Diagram ....................................................................... 279
Figure 22.2. UART1 Baud Rate Logic .................................................................... 280
Figure 22.3. UART Interconnect Diagram .............................................................. 281
Figure 22.4. 8-Bit UART Timing Diagram............................................................... 281
Figure 22.5. 9-Bit UART Timing Diagram............................................................... 282
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 283
23. Timers
Figure 23.1. T0 Mode 0 Block Diagram.................................................................. 290
Figure 23.2. T0 Mode 2 Block Diagram.................................................................. 291
www.DataSheet4U.com Figure 23.3. T0 Mode 3 Block Diagram.................................................................. 292
Figure 23.4. Tn Capture Mode Block Diagram ....................................................... 298
Figure 23.5. Tn Auto-reload Mode Block Diagram ................................................. 299
24. Programmable Counter Array
Figure 24.1. PCA Block Diagram............................................................................ 305
Figure 24.2. PCA Counter/Timer Block Diagram.................................................... 306
Figure 24.3. PCA Interrupt Block Diagram ............................................................. 307
Figure 24.4. PCA Capture Mode Diagram.............................................................. 308
Figure 24.5. PCA Software Timer Mode Diagram .................................................. 309
Figure 24.6. PCA High Speed Output Mode Diagram............................................ 310
Figure 24.7. PCA Frequency Output Mode ............................................................ 311
Figure 24.8. PCA 8-Bit PWM Mode Diagram ......................................................... 312
Figure 24.9. PCA 16-Bit PWM Mode...................................................................... 313
25. JTAG (IEEE 1149.1)
12 Rev. 1.4

12 Page





SeitenGesamt 70 Seiten
PDF Download[ C8051F047 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
C8051F040(C8051F040 - C8051F043) Mixed-Signal MCUCygnal
Cygnal
C8051F040(C8051F040 - C8051F047) 100-Pin Mixed-Signal MCUSilicon Laboratories
Silicon Laboratories
C8051F041(C8051F040 - C8051F047) 100-Pin Mixed-Signal MCUSilicon Laboratories
Silicon Laboratories
C8051F041(C8051F040 - C8051F043) Mixed-Signal MCUCygnal
Cygnal
C8051F042(C8051F040 - C8051F047) 100-Pin Mixed-Signal MCUSilicon Laboratories
Silicon Laboratories

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche