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C8051F022 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F022
Beschreibung (C8051F020 - C8051F023) 8K ISP FLASH MCU Family
Hersteller Silicon Laboratories
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Gesamt 70 Seiten
C8051F022 Datasheet, Funktion
C8051F020/1/2/3
8K ISP FLASH MCU Family
ANALOG PERIPHERALS
- SAR ADC
12-Bit (C8051F020/1)
10-Bit (C8051F022/3)
± 1 LSB INL
Programmable Throughput up to 100 ksps
Up to 8 External Inputs; Programmable as Single-Ended or
Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data-Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (± 3°C)
- 8-bit ADC
www.DataSheet4U.com Programmable Throughput up to 500 ksps
8 External Inputs
Programmable Amplifier Gain: 4, 2, 1, 0.5
- Two 12-bit DACs
Can Synchronize Outputs to Timers for Jitter-Free Wave-
form Generation
- Two Analog Comparators
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full- Speed, Non-
Intrusive In-Circuit/In-System Debugging
- Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Low-Cost, Complete Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25 MIPS Throughput with 25 MHz Clock
- 22 Vectored Interrupt Sources
MEMORY
- 4352 Bytes Internal Data RAM (4k + 256)
- 64k Bytes FLASH; In-System programmable in 512-byte
Sectors
- External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)
DIGITAL PERIPHERALS
- 8 Byte-Wide Port I/O (C8051F020/2); 5V tolerant
- 4 Byte-Wide Port I/O (C8051F021/3); 5V tolerant
- Hardware SMBus™ (I2C™ Compatible), SPI™, and
Two UART Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with
5 Capture/Compare Modules
- 5 General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer; Bi-directional Reset Pin
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16 MHz
- External Oscillator: Crystal, RC, C, or Clock
- Real-Time Clock Mode using Timer 3 or PCA
SUPPLY VOLTAGE .......................... 2.7V TO 3.6V
- Typical Operating Current: 10 mA @ 20 MHz
- Multiple Power Saving Sleep and Shutdown Modes
100-Pin TQFP and 64-Pin TQFP Packages Available
Temperature Range: -40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
VREF
10/12-bit
100ksps
ADC
12-Bit
DAC
12-Bit
DAC
8-bit
PGA 500ksps
ADC
++
--
VOLTAGE
COMPARATORS
DIGITAL I/O
UART0
UART1
SMBus
SPI Bus
Port 0
Port 1
Port 2
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Port 3
Port 4
Port 5
Port 6
Port 7
64 pin 100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
22
INTERRUPTS
64KB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
JTAG
CLOCK
SANITY
CIRCUIT CONTROL
Preliminary Rev. 1.4 12/03
Copyright © 2003 by Silicon Laboratories
C8051F020/1/2/3-DS14
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.






C8051F022 Datasheet, Funktion
C8051F020/1/2/3
18.3. SMBus Transfer Modes.................................................................................................187
18.3.1. Master Transmitter Mode ....................................................................................187
18.3.2. Master Receiver Mode.........................................................................................187
18.3.3. Slave Transmitter Mode.......................................................................................188
18.3.4. Slave Receiver Mode ...........................................................................................188
18.4. SMBus Special Function Registers ...............................................................................189
18.4.1. Control Register ...................................................................................................189
18.4.2. Clock Rate Register .............................................................................................192
18.4.3. Data Register........................................................................................................193
18.4.4. Address Register ..................................................................................................193
www.DataSheet4U.com 18.4.5. Status Register .....................................................................................................194
19. SERIAL PERIPHERAL INTERFACE BUS (SPI0) ........................................................197
19.1. Signal Descriptions........................................................................................................198
19.1.1. Master Out, Slave In (MOSI) ..............................................................................198
19.1.2. Master In, Slave Out (MISO) ..............................................................................198
19.1.3. Serial Clock (SCK) ..............................................................................................198
19.1.4. Slave Select (NSS)...............................................................................................198
19.2. SPI0 Operation ..............................................................................................................199
19.3. Serial Clock Timing ......................................................................................................200
19.4. SPI Special Function Registers .....................................................................................201
20. UART0 ..................................................................................................................................205
20.1.UART0 Operational Modes ..........................................................................................206
20.1.1. Mode 0: Synchronous Mode................................................................................206
20.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................207
20.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................208
20.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................209
20.2. Multiprocessor Communications...................................................................................210
20.3. Frame and Transmission Error Detection......................................................................211
21. UART1 ..................................................................................................................................215
21.1.UART1 Operational Modes ..........................................................................................216
21.1.1. Mode 0: Synchronous Mode................................................................................216
21.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................217
21.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................218
21.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................219
21.2. Multiprocessor Communications...................................................................................220
21.3. Frame and Transmission Error Detection......................................................................221
22. TIMERS................................................................................................................................225
22.1. Timer 0 and Timer 1......................................................................................................227
22.1.1. Mode 0: 13-bit Counter/Timer.............................................................................227
22.1.2. Mode 1: 16-bit Counter/Timer.............................................................................228
22.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload .................................................229
22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................230
22.2. Timer 2 .......................................................................................................................234
22.2.1. Mode 0: 16-bit Counter/Timer with Capture .......................................................235
22.2.2. Mode 1: 16-bit Counter/Timer with Auto-Reload ...............................................236
6 Rev. 1.4

6 Page









C8051F022 pdf, datenblatt
C8051F020/1/2/3
Table 15.1. FLASH Electrical Characteristics .....................................................................140
Figure 15.1. FLASH Program Memory Map and Security Bytes .........................................141
Figure 15.2. FLACL: FLASH Access Limit .........................................................................142
Figure 15.3. FLSCL: FLASH Memory Control ....................................................................143
Figure 15.4. PSCTL: Program Store Read/Write Control .....................................................144
16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145
Figure 16.1. EMI0CN: External Memory Interface Control .................................................147
Figure 16.2. EMI0CF: External Memory Configuration .......................................................147
Figure 16.3. Multiplexed Configuration Example.................................................................148
Figure 16.4. Non-multiplexed Configuration Example .........................................................149
www.DataSheet4U.com Figure 16.5. EMIF Operating Modes.....................................................................................150
Figure 16.6. EMI0TC: External Memory Timing Control ....................................................152
Figure 16.7. Non-multiplexed 16-bit MOVX Timing ...........................................................153
Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................154
Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing.................................155
Figure 16.10. Multiplexed 16-bit MOVX Timing .................................................................156
Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing .................................157
Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing.......................................158
Table 16.1. AC Parameters for External Memory Interface.................................................159
17. PORT INPUT/OUTPUT .....................................................................................................161
Figure 17.1. Port I/O Cell Block Diagram.............................................................................161
Table 17.1. Port I/O DC Electrical Characteristics ..............................................................161
Figure 17.2. Lower Port I/O Functional Block Diagram .......................................................162
Figure 17.3. Priority Crossbar Decode Table ........................................................................163
Figure 17.4. Priority Crossbar Decode Table ........................................................................166
Figure 17.5. Priority Crossbar Decode Table ........................................................................167
Figure 17.6. Crossbar Example: ............................................................................................169
Figure 17.7. XBR0: Port I/O Crossbar Register 0 .................................................................170
Figure 17.8. XBR1: Port I/O Crossbar Register 1 .................................................................171
Figure 17.9. XBR2: Port I/O Crossbar Register 2 .................................................................172
Figure 17.10. P0: Port0 Data Register ...................................................................................173
Figure 17.11. P0MDOUT: Port0 Output Mode Register.......................................................173
Figure 17.12. P1: Port1 Data Register ...................................................................................174
Figure 17.13. P1MDIN: Port1 Input Mode Register .............................................................174
Figure 17.14. P1MDOUT: Port1 Output Mode Register.......................................................175
Figure 17.15. P2: Port2 Data Register ...................................................................................175
Figure 17.16. P2MDOUT: Port2 Output Mode Register.......................................................175
Figure 17.17. P3: Port3 Data Register ...................................................................................176
Figure 17.18. P3MDOUT: Port3 Output Mode Register.......................................................176
Figure 17.19. P3IF: Port3 Interrupt Flag Register .................................................................177
Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register ...................................................179
Figure 17.21. P4: Port4 Data Register ...................................................................................180
Figure 17.22. P5: Port5 Data Register ...................................................................................180
Figure 17.23. P6: Port6 Data Register ...................................................................................181
Figure 17.24. P7: Port7 Data Register ...................................................................................181
12 Rev. 1.4

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