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C8051F002 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F002
Beschreibung (C8051F000 - C8051F007) Mixed-Signal 32KB ISP FLASH MCU Family
Hersteller Silicon Laboratories
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Gesamt 30 Seiten
C8051F002 Datasheet, Funktion
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mixed-Signal 32KB ISP FLASH MCU Family
a
ANALOG PERIPHERALS
- SAR ADC
12-Bit (C8051F000/1/2, C8051F005/6/7)
10-bit (C8051F010/1/2, C8051F015/6/7)
±1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (± 3°C)
- Two 12-bit DACs
www.DataSheet4U.c-om Two Analog Comparators
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
- Voltage Reference
2.4V; 15 ppm/°C
Available on External Pin
- Precision VDD Monitor/Brown-out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
- Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
- Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Low Cost Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25MIPS Throughput with 25MHz Clock
- 21 Vectored Interrupt Sources
MEMORY
- 256 Bytes Internal Data RAM (F000/01/02/10/11/12)
- 2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
- 32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
DIGITAL PERIPHERALS
- 4 Byte-Wide Port I/O; All are 5V tolerant
- Hardware SMBusTM (I2CTM Compatible), SPITM, and UART
Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
- Four General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer
- Bi-directional Reset
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16MHz
- External Oscillator: Crystal, RC,C, or Clock
- Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
SUPPLY VOLTAGE ........................2.7V to 3.6V
- Typical Operating Current: 12.5mA @ 25MHz
- Multiple Power Saving Sleep and Shutdown Modes
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: –40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
SAR
ADC
12-Bit
DAC
12-Bit
DAC
VREF
+
+-
-
VOLTAGE
COMPARATORS
DIGITAL I/O
PCA
SMBus
SPI Bus
UART
Timer 0
Timer 1
Timer 2
Timer 3
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
32KB
ISP FLASH
CLOCK
CIRCUIT
JTAG
DEBUG
CIRCUITRY
256/2304 B
21
SANITY
SRAM INTERRUPTS CONTROL
Rev. 1.7 11/03
Copyright © 2003 by Silicon Laboratories






C8051F002 Datasheet, Funktion
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 18.2. Oscillator Frequencies for Standard Baud Rates ........................................................................136
Figure 18.8. SBUF: Serial (UART) Data Buffer Register.............................................................................136
Figure 18.9. SCON: Serial Port Control Register..........................................................................................137
19. TIMERS ............................................................................................................................138
19.1. Timer 0 and Timer 1 ........................................................................................................................138
Figure 19.1. T0 Mode 0 Block Diagram........................................................................................................139
Figure 19.2. T0 Mode 2 Block Diagram........................................................................................................140
Figure 19.3. T0 Mode 3 Block Diagram........................................................................................................141
Figure 19.4. TCON: Timer Control Register.................................................................................................142
Figure 19.5. TMOD: Timer Mode Register...................................................................................................143
Figure 19.6. CKCON: Clock Control Register..............................................................................................144
Figure 19.7. TL0: Timer 0 Low Byte ............................................................................................................145
Figure 19.8. TL1: Timer 1 Low Byte ............................................................................................................145
www.DataSheet4U.com Figure 19.9. TH0: Timer 0 High Byte ...........................................................................................................145
Figure 19.10. TH1: Timer 1 High Byte .........................................................................................................145
19.2. Timer 2 ............................................................................................................................................146
Figure 19.11. T2 Mode 0 Block Diagram......................................................................................................147
Figure 19.12. T2 Mode 1 Block Diagram......................................................................................................148
Figure 19.13. T2 Mode 2 Block Diagram......................................................................................................149
Figure 19.14. T2CON: Timer 2 Control Register..........................................................................................150
Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte ......................................................................151
Figure 19.16. RCAP2H: Timer 2 Capture Register High Byte .....................................................................151
Figure 19.17. TL2: Timer 2 Low Byte ..........................................................................................................151
Figure 19.18. TH2: Timer 2 High Byte .........................................................................................................151
19.3. Timer 3 ............................................................................................................................................152
Figure 19.19. Timer 3 Block Diagram...........................................................................................................152
Figure 19.20. TMR3CN: Timer 3 Control Register ......................................................................................152
Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte ....................................................................153
Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte ...................................................................153
Figure 19.23. TMR3L: Timer 3 Low Byte ....................................................................................................153
Figure 19.24. TMR3H: Timer 3 High Byte ...................................................................................................153
20. PROGRAMMABLE COUNTER ARRAY....................................................................154
Figure 20.1. PCA Block Diagram .................................................................................................................154
20.1. Capture/Compare Modules ..............................................................................................................155
Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules ...........................................155
Figure 20.2. PCA Interrupt Block Diagram...................................................................................................155
Figure 20.3. PCA Capture Mode Diagram ....................................................................................................156
Figure 20.4. PCA Software Timer Mode Diagram........................................................................................157
Figure 20.5. PCA High Speed Output Mode Diagram..................................................................................157
Figure 20.6. PCA PWM Mode Diagram .......................................................................................................158
20.2. PCA Counter/Timer.........................................................................................................................159
Table 20.2. PCA Timebase Input Options.....................................................................................................159
Figure 20.7. PCA Counter/Timer Block Diagram.........................................................................................159
20.3. Register Descriptions for PCA ........................................................................................................160
Figure 20.8. PCA0CN: PCA Control Register ...............................................................................................160
Figure 20.9. PCA0MD: PCA Mode Register ................................................................................................161
Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers......................................................................162
Figure 20.11. PCA0L: PCA Counter/Timer Low Byte .................................................................................163
Figure 20.12. PCA0H: PCA Counter/Timer High Byte ................................................................................163
Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte ........................................................................163
Figure 20.14. PCA0CPHn: PCA Capture Module High Byte.......................................................................163
21. JTAG (IEEE 1149.1) ........................................................................................................164
Figure 21.1. IR: JTAG Instruction Register ..................................................................................................164
21.1. Boundary Scan.................................................................................................................................165
Rev. 1.7
6

6 Page









C8051F002 pdf, datenblatt
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.1. CIP-51TM CPU
1.1.1. Fully 8051 Compatible
The C8051F000 family utilizes Silicon Laboratories’ proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51TM instruction set. Standard 803x/805x assemblers and compilers can be used to
develop software. The core has all the peripherals included with a standard 8052, including four 16-bit
counter/timers, a full-duplex UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR)
address space, and four byte-wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
www.DataSheet4U.ceoxmecute with a maximum system clock of 12-to-24MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with only four instructions taking more than four system clock
cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:
Instructions 26
50
5
14
7
3
1
2
Clocks to Execute 1
2 2/3 3 3/4 4 4/5 5
1
8
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.4. Comparison of Peak MCU Execution Speeds
25
20
15
10
5
Silicon Labs Microchip Philips ADuC812
CIP-51 PIC17C75x 80C51
8051
(25MHz clk) (33MHz clk) (33MHz clk) (16MHz clk)
Rev. 1.7
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