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Teilenummer | EDS6432CFBH |
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Beschreibung | 64M bits SDRAM | |
Hersteller | Elpida Memory | |
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Gesamt 30 Seiten DATA SHEET
64M bits SDRAM
EDS6432AFBH, EDS6432CFBH
(2M words × 32 bits)
Description
The EDS6432AFBH, EDS6432CFBH are 64M bits
SDRAMs organized as 524,288 words × 32 bits × 4
banks. All inputs and outputs are synchronized with
www.DataSheet4Ut.hcoempositive edge of the clock.
Supply voltages are 3.3V (EDS6432AFBH) and 2.5V
(EDS6432CFBH).
They are packaged in 90-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×32 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 NC
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 NC
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A10
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0497E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
EDS6432AFBH, EDS6432CFBH
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
[EDS6432AF]
Parameter
Symbol min.
max.
Unit Test condition
Note
Input leakage current
ILI –1
1
µA 0 ≤ VIN ≤ VDD
Output leakage current
ILO –1.5
1.5
µA 0 ≤ VOUT ≤ VDD, DQ = disable
Output high voltage
VOH
2.4
—
V IOH = –2 mA
Output low voltage
VOL
—
0.4 V IOL = 2 mA
[EDS6432CF]
Parameter
Input leakage current
www.DataSheet4UO.cuotmput leakage current
Output high voltage
Output low voltage
Symbol
ILI
ILO
VOH
VOL
min.
–1
–1.5
2.0
—
max.
1
1.5
—
0.4
Unit Test condition
Note
µA 0 ≤ VIN ≤ VDD
µA 0 ≤ VOUT ≤ VDD, DQ = disable
V IOH = –1 mA
V IOL = 1 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V) [EDS6432AF]
(TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V) [EDS6432CF]
Parameter
Symbol Pins
min. typ.
max.
Unit Notes
Input capacitance
CI1 CLK
1.5 —
3.5 pF 1, 2, 4
Data input/output
capacitance
CI2
CI/O
Address, CKE, /CS,
/RAS, /CAS, /WE,
DQM
DQ
1.5
3.0
—
—
3.8 pF 1, 2, 4
6.5 pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V(EDS6432AFBH) and 1.2V (EDS6432CFBH) bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
Data Sheet E0497E20 (Ver. 2.0)
6
6 Page EDS6432AFBH, EDS6432CFBH
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function
Symbol n – 1 n
/CS /RAS /CAS /WE BA1 BA0 A10
Device deselect
DESL
H×
H
×
×
×
×
×
×
No operation
NOP
H× L
HHH×
×
×
Burst stop
BST H × L H H L × × ×
Read
READ H × L H L H V V L
Read with auto precharge
READA H × L
HL
HVVH
Write
WRIT
H× L
HL
L
V
V
L
www.DataSheet4UW.corimte with auto precharge WRITA H × L H L L V V H
Bank activate
ACT H × L L H H V V V
Precharge select bank
PRE H × L L H L V V L
Precharge all banks
PALL
H× L
L
HL
×
×
H
Mode register set
MRS
H× L
L
L
L
L
L
L
Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input.
A0 to
A10
×
×
×
V
V
V
V
V
×
×
V
Device deselect command [DESL]
When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal
status is held.
No operation [NOP]
This command is not an execution command. However, the internal operations continue.
Burst stop command [BST]
This command can stop the current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. In addition, the start address of burst read is determined by the column
address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
Column address strobe and write command [WRIT]
This command starts a write operation. When the burst write mode is selected, the column address (see Address
Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the
single write mode is selected, data is only written to the location specified by the column address (see Address Pins
Table in Pin Function) and the bank select address (BA0, BA1).
Write with auto-precharge [WRITA]
This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a
single write operation.
Data Sheet E0497E20 (Ver. 2.0)
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EDS6432CFBH Schematic.PDF ] |
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