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AD5626 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5626
Beschreibung 12-Bit nanoDAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD5626 Datasheet, Funktion
FEATURES
8-lead MSOP and 8-lead LFCSP packages
Complete voltage output with internal reference
1 mV/bit with 4.095 V full scale
5 V single-supply operation
No external components required
3-wire serial interface, 20 MHz data loading rate
www.DataSheeLt4oUw.cpoomwer: 2.5 mW
APPLICATIONS
Portable instrumentation
Digitally controlled calibration
Servo controls
Process control equipment
PC peripherals
5 V, 12-Bit nanoDAC, Serial Interface
in MSOP and LFCSP Packages
AD5626
GENERAL DESCRIPTION
The AD5626, a member of the nanoDAC® family, is a complete
serial input, 12-bit, voltage output digital-to-analog converter
(DAC) designed to operate from a single 5 V supply. It contains
the DAC, input shift register and latches, reference, and a rail-
to-rail output amplifier. The AD5626 monolithic DAC offers
the user low cost and ease of use in 5 V only systems.
Coding for the AD5626 is natural binary with the MSB loaded
first. The output op amp can swing to either rail and is set to a
range of 0 V to 4.095 V for a one-millivolt-per-bit resolution. It
is capable of sinking and sourcing 5 mA. An on-chip reference
is laser trimmed to provide an accurate full-scale output voltage
of 4.095 V.
This part features a serial interface that is high speed, three-
wire, DSP compatible with data in (SDIN), clock (SCLK), and
load strobe (LDAC). There is also a chip-select pin for
connecting multiple DACs.
The CLR input sets the output to zero scale at power on or upon
user demand.
The AD5626 is specified over the extended industrial tempera-
ture range (–40°C to +85°C). The AD5626 is available in MSOP
and LFCSP surface-mount packages.
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5626
REF
LDAC
CLR
DAC REGISTER
12-BIT DAC
OUTPUT
BUFFER
VOUT
INPUT
REGISTER
CS SCLK SDIN
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.






AD5626 Datasheet, Funktion
AD5626
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
8 VOUT
CS 2 AD5626 7 GND
SCLK 3 TOP VIEW 6 CLR
(Not to Scale)
SDIN 4
5 LDAC
Figure 3. 8-Lead MSOP Pin Configuration
VDD 1
CS 2
SCLK 3
SDIN 4
AD5626
TOP VIEW
(Not to Scale)
8 VOUT
7 GND
6 CLR
5 LDAC
Figure 4. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic
Description
1 VDD
www.Data2Sheet4U.comCS
Positive Supply. Nominal value 5 V ± 5%.
Chip Select. Active low input.
3 SCLK
Clock Input. Clock input for the internal serial input shift register.
4 SDIN
Serial Data Input. Data on this pin is clocked into the internal serial register on positive clock edges of the
SCLK pin. The most significant bit (MSB) is loaded first.
5 LDAC
Serial Register Data Write to DAC Register. Active low input that writes the serial register data into the DAC
register. Asynchronous input.
6 CLR
Clear DAC Register. Active low digital input that clears the DAC register to zero, setting the DAC to minimum
scale. Asynchronous input.
7 GND
Ground. Analog ground for the DAC. This also serves as the digital logic ground reference voltage.
8 VOUT
Voltage Output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature, and
power supply variations.
Table 5. Control Logic Truth Table1
CS2, 3 CLK2 CLR LD4 Serial Shift Register Function
HX
H H No effect
LL
LH
L +
+ L
HX
HX
HX
HX
H H No effect
H H No effect
H H Shift-register-data advanced one bit
H H Shift-register-data advanced one bit
H – No effect
H L No effect
L X No effect
+ H No effect
1 + indicates a positive logic transition; – indicates a negative logic transition; X = don’t care.
2 CS and CLK are interchangeable.
3 Returning CS high avoids an additional false clock of serial data input.
4 Do not clock in serial data while LD is low.
DAC Register Function
Latched
Latched
Latched
Latched
Latched
Updated with current shift register contents
Transparent
Loaded with all zeros
Latched all zeros
Rev. 0 | Page 6 of 20

6 Page









AD5626 pdf, datenblatt
AD5626
APPLICATIONS INFORMATION
POWER SUPPLIES, BYPASSING, AND GROUNDING
All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the AD5626 has been designed for 5 V applications, it
is ideal for those applications under microprocessor or micro-
computer control. In these applications, digital noise is prevalent;
therefore, special care must be taken to ensure that its inherent
precision is maintained by exercising particularly good engineering
judgment when addressing the power supply, grounding, and
bypassing issues using the AD5626.
www.DataUShseeeat4wUe.lcl-ofmiltered and regulated power supply for the AD5626.
The device has been completely characterized for a 5 V supply
with a tolerance of ±5%. Because a 5 V logic supply is almost
universally available, it is not recommended to connect the
DAC directly to an unfiltered logic supply without careful
filtering. Tapping a logic circuit supply for the DAC supply
is unwise because fast logic with nanosecond transition edges
induce high current pulses. The high transient current pulses
can generate glitches hundreds of millivolts in amplitude due
to wiring resistances and inductances. This high frequency
noise corrupts the analog circuits internal to the DAC and
causes errors.
Even though their spike noise is lower in amplitude, directly
tapping the output of a 5 V system supply can cause errors
because these supplies are of the switching regulator type that
can and do generate a great deal of high frequency noise. There-
fore, power the DAC and any associated analog circuitry directly
from the system power supply outputs using appropriate filtering.
Figure 25 illustrates how a clean, analog-grade supply can be
generated from a 5 V logic supply using a differential LC filter
with separate power supply and return lines. With the values
shown, this filter can easily handle 100 mA of load current
without saturating the ferrite cores. Higher current capacity
can be achieved with larger ferrite cores. For lowest noise, all
electrolytic capacitors should be of the low equivalent series
resistance (ESR) type.
TTL/CMOS
LOGIC
CIRCUITS
FERRITE BEADS:
2 TURNS
+ 100µF
+ 10-20µF
ELECT.
TANT.
+5V
0.1µF
CER.
+5V
RETURN
5V
POWER SUPPLY
Figure 25. Properly Filtering a 5 V Logic Supply Yields a High Quality
Analog Supply
To fit the AD5626 in an 8-lead package, only one ground
connection to the device is accommodated. The ground
connection of the DAC serves as the return path for supply
currents as well as the reference point for the digital input
thresholds. The ground connection also serves as the supply rail
for the internal voltage reference and the output amplifier.
Therefore, to minimize errors, connect the ground connection
of the AD5626 to a high quality analog ground, such as the one
previously described. Generous bypassing of the DACs supply
effectively reduces supply line induced errors. Local supply
bypassing consisting of a 10 μF tantalum electrolytic capacitor
in parallel with a 0.1 μF ceramic capacitor is recommended.
Connect the decoupling capacitors between the DAC supply
pin (Pin 1) and the analog ground (Pin 7).
Figure 26 shows how the ground and bypass connections
should be made to the AD5626.
5V
CS 2
1
VDD
CLR 6 AD5626
+ 10µF
0.1µF
LDAC
SCLK
5
3
VOUT 8
VOUT
SDIN
4
GND
7
TO ANALOG GROUND
Figure 26. Recommended Grounding and Bypassing Scheme for the AD5626
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD5626. As shown
in Figure 27, the AD5626 is designed to drive loads as low as
2 kΩ in parallel with 500 pF. The code table for this operation is
provided in Table 6.
5V
0.1µF
10µF
+
CS 2
1
VDD
CLR 6 AD5626
LDAC
5
VOUT 8
0V VOUT 4.095V
SCLK
3
2k500pF
SDIN
4
GND
7
Figure 27. Unipolar Output Operation
Table 6. Unipolar Code Table
Hexadecimal Number Decimal Number
in DAC Register
in DAC Register
FFF 4095
801 2049
800 2048
7FF 2047
000 0
Analog Output
Voltage (V)
4.095
2.049
2.048
2.047
0
Rev. 0 | Page 12 of 20

12 Page





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