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PDF CLC417 Data sheet ( Hoja de datos )
| Número de pieza | CLC417 | |
| Descripción | Programmable Gain Buffer | |
| Fabricantes | National Semiconductor | |
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N
CLC417
Dual Low-Power, Programmable Gain Buffer
September 1998
General Description
The CLC417 is a dual, low-cost, high-speed (120MHz) buffer which
features user-programmable gains of +2, +1, and -1V/V. The
CLC417’s high 60mA output current, coupled with its ultra-low
39mW per channel power consumption makes it the ideal choice for
www.DataSheedt4eUm.caomnding applications that are sensitive to both power and cost.
Utilizing National’s proven architectures, this dual current feedback
amplifier surpasses the performance of alternate solutions with a
closed-loop design that produces new standards for buffers in gain
accuracy, input impedance, and input bias currents. The CLC417’s
internal feedback network provides an excellent gain accuracy of
0.1%. High source impedance applications will benefit from the
CLC417’s 6MΩ input impedance along with its exceptionally low
100nA input bias current.
With exceptional gain flatness and low differential gain and phase
errors, the CLC417 is very useful for professional video processing
and distribution. A 120MHz -3dB bandwidth coupled with a 400V/µs
slew rate also make the CLC417 a perfect choice in cost-sensitive
applications such as video monitors, fax machines, copiers, and
CATV systems. Back-terminated video applications will be
enhanced by a gain of +2 configuration which requires no external
gain components reducing costs and board space.
Features
s 0.01%, 0.03° DG, Dφ
s High output current: 60mA
s High input impedance: 6MΩ
s Gains of +1, +2 with no external
components
s Low power
s Very low input bias currents: 100nA
s Excellent gain accuracy: 0.1%
s High speed: 120MHz -3dB BW
s Low-cost
Applications
s Desktop video systems
s Video distribution
s Flash A/D driver
s High-speed line driver
s High-source impedance applications
s Professional video processing
s High resolution monitors
Frequency Response (AV = +2V/V)
Typical Application
Differential Input/Differential Output Amplifier
-5V
Vin2 0.1µF 6.8µF
OUT1
CLC417
250Ω 250Ω
Vout2
-IN1
Vin1
6.8µF 0.1µF
+5V
250Ω 250Ω
Vout1
Vout1 – Vout2 = (Vin1 – Vin2) x 2
+IN1
-VCC
© 1998 National Semiconductor Corporation
Printed in the U.S.A.
Pinout
DIP & SOIC
250Ω
250Ω -
+
250Ω 250Ω
+VCC
OUT2
-IN2
+IN2
http://www.national.com
1 page  
Channel Matching
Channel matching and crosstalk efficiency are largely
dependent on board layout. The layout of National’s dual
amplifier evaluation boards are optimized to produce
maximum channel matching and isolation. Typical
channel matching for the CLC417 is shown in Figure 3.
www.DataSheet4U.com
Av = +2
RL = 100Ω
Vo = 2Vpp
Channel B
Channel A
Channel B
0
Channel A
-90
-180
-270
-360
-450
1 10
100
Frequency (MHz)
Figure 3: Channel Matching
The CLC417’s channel-to-channel isolation is better than
70dB for input frequencies of 4MHz. Input referred
crosstalk vs. frequency is illustrated in Figure 4.
-20
-40
-60
-80
-100
-120
1
10
Frequency (MHz)
100
Figure 4: Input Referred Crosstalk vs. Frequency
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC417 will
improve stability. The Rs vs. Capacitive Load
plot, in the Typical Performance section, gives the
recommended series resistance value for optimum
flatness at various capacitive loads.
Power Dissipation
The power dissipation of an amplifier can be described in
two conditions:
s Quiescent Power Dissipation -
PQ (No Load Condition)
s Total Power Dissipation -
PT (with Load Condition)
The following steps can be taken to determine the power
consumption for each CLC417 amplifier:
1. Determine the quiescent power
PQ = (VCC - VEE) • ICC
2. Determine the RMS power at the output stage
PO = (VCC - Vload) (Iload), where Vload and Iload
are the RMS voltage and current across the
external load.
3. Determine the total RMS power
PT = PQ + PO
Add the total RMS powers for both channels to determine
the power dissipated by the dual.
The maximum power that the package can dissipate at a
given temperature is illustrated in the Power Derating
curves in the Typical Performance section. The power
derating curve for any package can be derived by utiliz-
ing the following equation:
P = (175° − Tamb)
θ JA
where: Tamb = Ambient temperature (°C)
θJA = Thermal resistance, from junction to
ambient, for a given package (°C/W)
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC417 (CLC730038 - DIP,
CLC730036 - SOIC) and suggests their use as a guide
for high frequency layout and as an aid for device testing
and characterization.
Supply bypassing is required for best performance. The
bypass capacitors provide a low impedance return
current path at the supply pins. They also provide high
frequency filtering on the power supply traces. Other
layout factors play a major role in high frequency
performance. The following are recommended as a basis
for high frequency layout:
1. Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
2. Place the 6.8µF capacitors within 0.75 inches
of the power pins.
3. Place the 0.1µF capacitors less than 0.1
inches from the power pins.
4. Remove the ground plane near the input
and output pins to reduce parasitic
capacitance.
5. Minimize all trace lengths to reduce series
inductances.
Additional information is included in the evaluation board
literature.
Special Evaluation Board Considerations
To optimize off-isolation of the CLC417, cut the Rf trace
on both the 730038 and 730036 evaluation boards. This
cut minimizes capacitive feedthrough between the input
and output. Figure 5 indicates the alterations
recommended to improve off-isolation.
5 http://www.national.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CLC417.PDF ] | |
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