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Teilenummer | GL811S |
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Beschreibung | USB 2.0 to ATA / ATAPI Bridge Controller | |
Hersteller | GENESYS LOGIC | |
Logo | ||
Gesamt 30 Seiten www.DataSheet4U.com
Genesys Logic, Inc.
GL811S
USB 2.0 to ATA/ATAPI
Bridge Controller
Datasheet
Revision 1.02
Apr. 13, 2007
GL811S USB2.0 to ATA/ATAPI Bridge Controller
LIST OF TABLES
TABLE 3.1 - 48 PIN LIST..................................................................................................... 11
TABLE 3.2 - 64 PIN LIST..................................................................................................... 11
TABLE 3.3 – 48 PIN DESCRIPTIONS.................................................................................... 12
TABLE 3.4 - 64 PIN DESCRIPTIONS .................................................................................... 13
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TABLE 6.1 - MAXIMUM RATINGS ...................................................................................... 18
TABLE 6.2 - TEMPERATURE CONDITIONS ......................................................................... 18
TABLE 6.3 - I/O TYPE DIGITAL PINS .................................................................................. 18
TABLE 6.4 - D+/ D-............................................................................................................. 19
TABLE 6.5 - SWITCHING CHARACTERISTICS .................................................................... 19
TABLE 6.5 - ULTRA DMA DATA BURST TIMING REQUIREMENTS ..................................... 27
TABLE 8.1 - ORDERING INFORMATION ............................................................................. 37
©2007 Genesys Logic Inc. - All rights reserved.
Page 6
6 Page GL811S USB2.0 to ATA/ATAPI Bridge Controller
15 DD7
16 NC
B 31 X_POWER P 47 INTRQ I 63
32 XO
B 48 DMACK_ O 64
F_LED
H_LED
B
B
3.3 Pin Descriptions
Table 3.3 – 48 Pin Descriptions
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Pin Name
VREF
DM
DP
XO
XI
RESET#
TEST
USB Interface
Pin# Type
Description
21 A Reference Resistor
18 B HS D-
19 B HS D+
24 B Crystal output
25 I Crystal input
15
I External reset
(pu)
26
I Test mode Input
(pd)
Pin Name
DD0~15
HD_RST#
CS1_, CS0_
DA0~2
INTRQ
DMACK_
IORDY
DIOR_
DIOW_
DMARQ
Pin#
43,45,47,
2,5,8,10,1
2,11,9,6,4,
1,46,44,
41
13
27,31
33,34,32
35
36
37
38
39
40
Type
B
(pd)
O
O
O
I
(pd)
O
I
(pu)
O
O
I
(pd)
ATA/ATAPI Interface
Description
IDE Data Bus
Device Reset
Chip Select #1,#0
IDE Address #2,#1,#0
IDE interrupt input
IDE Acknowledge
IDE Ready
IDE read signal
IDE write signal
IDE request
©2007 Genesys Logic Inc. - All rights reserved.
Page 12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
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