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ADC774 Schematic ( PDF Datasheet ) - Burr-Brown

Teilenummer ADC774
Beschreibung Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown
Logo Burr-Brown Logo 




Gesamt 7 Seiten
ADC774 Datasheet, Funktion
® ADC774
www.DataSheet4U.com
Microprocessor-Compatible
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q COMPLETE 12-BIT A/D CONVERTER WITH
REFERENCE, CLOCK, AND 8-, 12-, or 16-
BIT MICROPROCESSOR BUS INTERFACE
q ALTERNATE SOURCE FOR HI774 A/D
CONVERTER: 8.5µs Conversion Time,
150ns Bus Access Time
q FULLY SPECIFIED FOR OPERATION ON
±12V OR ±15V SUPPLIES
q NO MISSING CODES OVER
TEMPERATURE:
0°C to +75°C: ADC774J, K
–55°C to +125°C: ADC774SH, TH
DESCRIPTION
The ADC774 is a 12-bit successive approximation
analog-to-digital converter, utilizing state-of-the-art
CMOS and laser-trimmed bipolar die custom-designed
for freedom from latch-up and for optimum AC per-
formance. It is complete with a self-contained +10V
reference, internal clock, digital interface for micropro-
cessor control, and three-state outputs.
The reference circuit, containing a buried zener, is laser-
trimmed for minimum temperature coefficient. The
clock oscillator is current-controlled for excellent sta-
bility over temperature. Full-scale and offset errors may
be externally trimmed to zero. Internal scaling resistors
are provided for the selection of analog input signal
ranges of 0V to +10V, 0V to +20V, ±5V, and ±10V.
The converter may be externally programmed to pro-
vide 8- or 12-bit resolution. The conversion time for 12
bits is factory set for 8.5µs maximum.
Output data are available in a parallel format from TTL-
compatible three-state output buffers. Output data are
coded in straight binary for unipolar input signals and
bipolar offset binary for bipolar input signals.
The ADC774, available in both industrial and military
temperature ranges, requires supply voltages of +5V
and ±12V or ±15V. It is packaged in a 28-pin plastic
DIP, or a hermetic side-brazed ceramic DIP.
Control
Inputs
Bipolar
Offset
20V Range
10V Range
Reference
Input
Reference
Output
Control Logic
Clock
Comparator
12-Bit D/A
Converter
10V
Reference
Status
Parallel
Data
Output
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1988 Burr-Brown Corporation
PDS-835E
Printed in U.S.A. March, 1992






ADC774 Datasheet, Funktion
Figure 1 illustrates timing when conversion is initiated by an
R/C pulse which goes low and returns to the high state
during the conversion. In this case, the three-state outputs
go to the high-impedance state in response to the falling
edge of R/C and are enabled for external access of the data
after completion of the conversion. Figure 2 illustrates the
timing when conversion is initiated by a positive R/C pulse.
In this mode the output data from the previous conversion is
enabled during the positive portion of R/C. A new conver-
sion is started on the falling edge of R/C, and the three-state
outputs return to the high-impedance state until the next
occurrence of a high R/C pulse. Timing specifications for
stand-alone operation are listed in Table III.
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the AO input, which is latched upon receipt of a conver-
sion start transition (described below). If AO is latched high,
the conversion continues for 8 bits. The full 12-bit conver-
sion will occur if AO is low. If all 12 bits are read following
an 8-bit conversion, the 3 LSBs (DB0–DB2) will be low
(logic 0) and DB3 will be high (logic 1). AO is latched
because it is also involved in enabling the output buffers. No
other control inputs are latched.
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CE
tSSC
CS
tSRC
R/C
AO
tSAC
STS
DB11–
DB0
tHEC
tHSC
tHRC
tHAC
tDSC
tC
High Impedance
FIGURE 3. Conversion Cycle Timing.
CE
CS
R/C
AO
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
STS
tHS tHD
DB11–
DB0
High-Z
tDD
Data Valid
tHL
FIGURE 4. Read Cycle Timing.
SYMBOL
PARAMETER
tDSC
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
tC
Read Mode
t
DD
tHD
t
HL
tSSR
t
SAR
tHSR
tHRR
tHAR
tHS
STS Delay from CE
CE Pulse Width
CS to CE Setup time
CS low during CE high
R/C to CE setup
R/C low during CE high
AO to CE setup
AO valid during CE high
Conversion time
12-bit cycle at 25°C
0 to +75°C
–55°C to +125°C
8-bit cycle at 25°C
0 to +75°C
–55° to +125°C
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
CS valid after CE low
R/C high after CE low
AO valid after CE low
STS delay after data valid
TABLE IV. Timing Specifications.
®
ADC774
MIN
50
50
50
50
50
0
50
25
50
0
0
0
50
6
TYP
60
30
20
20
0
20
20
7.5
5
75
35
100
0
MAX
200
8.5
9.0
9.5
5.3
5.6
6
150
150
150 375
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns

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