Datenblatt-pdf.com


W83977EG Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83977EG
Beschreibung WINBOND ISA I/O
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W83977EG Datasheet, Funktion
www.DataSheet4U.com
WINBOND
ISA I/O
W83977EF
W83977EG






W83977EG Datasheet, Funktion
W83977EF-AW/W83977EG-AW
14.
www.DataSheet4U.com
15.
16.
17.
18.
13.3.5 EPP Data or Address Write Cycle Timing Parameters ...............................................120
13.3.6 Parallel Port FIFO Timing Parameters........................................................................121
13.3.7 ECP Parallel Port Forward Timing Parameters ..........................................................121
13.3.8 ECP Parallel Port Reverse Timing Parameters ..........................................................121
13.3.9 KBC Timing Parameters.............................................................................................122
13.3.10 GPIO Timing Parameters ...........................................................................................123
13.3.11 Keyboard/Mouse Timing Parameters .........................................................................123
TIMING WAVEFORMS ........................................................................................................... 124
14.1 14.1 FDC..................................................................................................................... 124
14.2 UART/Parallel ............................................................................................................. 125
14.2.1 Modem Control Timing ...............................................................................................126
14.3 Parallel Port ................................................................................................................ 127
14.3.1 Parallel Port Timing ....................................................................................................127
14.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) ................................................128
14.3.3 EPP Data or Address Write Cycle (EPP Version 1.9).................................................129
14.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) ................................................130
14.3.5 EPP Data or Address Write Cycle (EPP Version 1.7).................................................131
14.3.6 Parallel Port FIFO Timing ...........................................................................................131
14.3.7 ECP Parallel Port Forward Timing..............................................................................132
14.3.8 ECP Parallel Port Reverse Timing..............................................................................132
14.4 KBC............................................................................................................................. 133
14.4.1 Write Cycle Timing .....................................................................................................133
14.4.2 Read Cycle Timing .....................................................................................................133
14.4.3 Receive Data from K/B ...............................................................................................134
14.4.4 Input Clock .................................................................................................................134
14.4.5 Send Data to Mouse...................................................................................................134
14.4.6 Receive Data from Mouse ..........................................................................................134
14.5 GPIO Write Timing Diagram ....................................................................................... 135
14.5.1 Master Reset (MR) Timing .........................................................................................135
14.6 Keyboard/Mouse Wake-up Timing ............................................................................. 135
APPLICATION CIRCUITS ...................................................................................................... 136
15.1 Parallel Port Extension FDD ....................................................................................... 136
15.2 Parallel Port Extension 2FDD ..................................................................................... 137
15.3 Four FDD Mode .......................................................................................................... 137
ORDERING INFORMATION .................................................................................................. 138
HOW TO READ THE TOP MARKING.................................................................................... 138
PACKAGE DIMENSIONS ....................................................................................................... 139
Publication Release Date: Apr. 2006
-V- Revision 1.2

6 Page









W83977EG pdf, datenblatt
W83977EF-AW/W83977EG-AW
Host Interface , continted.
SYMBOL
DRQ0
GP17
(PLEDO)
P14
SCI#
DACK1#
www.DataSheet4U.comDRQ1
DACK2#
DRQ2
DACK3#
DRQ3
PIN
121
122
123
124
125
126
127
TC 128
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
GP14
99
98
97
96
95
94
92
100
101
102
103
(GPACS1#)
(P17)
PLEDO
IRQ15
104
GP15
(GPACS2#)
(P12)
WDT
CLKIN
1
I/O
OUT12t
I/O12t
I/O12t
OUT12t
INts
OUT12t
INts
OUT12t
INts
OUT12t
INts
OUT12t
OUT12t
OUT12t
OUT12t
OUT12t
OUT12t
OUT12t
OUT12t
OUT12t
OUT12t
OUT12t
I/O12t
OUT12t
OUT12t
I/O12t
OUT12t
INt
FUNCTION
DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default)
General purpose I/O port 1bit 7. (CR2C bit 7_6 = 01)
Alternate Function from GP17: Power LED output.
KBC P14 I/O port (CR2C bit 7_6 = 10)
System Control Interrupt (CR2C bit 7_6 = 11)
DMA Channel 1 Acknowledge signal
DMA Channel 1 request signal
DMA Channel 2 Acknowledge signal
DMA Channel 2 request signal
DMA Channel 3 Acknowledge signal
DMA Channel 3 request signal
Terminal Count. When active, this pin indicates termination of
a DMA transfer.
Interrupt request 1
Interrupt request 3
Interrupt request 4
Interrupt request 5
Interrupt request 6
Interrupt request 7
Interrupt request 9
Interrupt request 10
Interrupt request 11
Interrupt request 12
Interrupt request 14. (CR2C bit 1_0 = 00, default)
General purpose I/O port 1 bit 4. (CR2C bit 1_0 = 01)
Alternate Function 1 from GP14: General purpose address
decode output.
Alternate Function 2 from GP14: KBC P17 I/O port.
Power LED output. (CR2C bit 1_0 = 10)
Interrupt request 15.(CR2C bit 3_2 = 00, default)
General purpose I/O port 1 bit 5. (CR2C bit 3_2 = 01)
Alternate Function 1 from GP15: General purpose address
write enable output.
Alternate Function 2 from GP15: KBC P12 I/O port.
Watch-Dog timer output. (CR2C bit 3_2 = 10)
24 or 48 MHz clock input, selectable through bit 5 of CR24.
-10-

12 Page





SeitenGesamt 30 Seiten
PDF Download[ W83977EG Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
W83977EFWINBOND I/OWinbond
Winbond
W83977EF-AWWINBOND I/OWinbond
Winbond
W83977EF-PWWINBOND I/OWinbond
Winbond
W83977EGWINBOND ISA I/OWinbond
Winbond

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche