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PDF ADN2811 Data sheet ( Hoja de datos )
| Número de pieza | ADN2811 | |
| Descripción | OC-48/OC-48 FEC Clock and Data Recovery IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a OC-48/OC-48 FEC Clock and Data Recovery IC
with Integrated Limiting Amp
ADN2811
FEATURES
Meets SONET Requirements for Jitter Transfer/
Generation/Tolerance
Quantizer Sensitivity: 4 mV Typ
Adjustable Slice Level: ؎100 mV
1.9 GHz Minimum Bandwidth
Patented Clock Recovery Architecture
Loss of Signal Detect Range: 3 mV to 15 mV
www.DataSheet4US.cionmgle Reference Clock Frequency for Both Native
SONET and 15/14 (7%) Wrapper Rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK LVPECL/LVDS/LVCMOS/LVTTL
Compatible Inputs (LVPECL/LVDS Only at 155.52 MHz)
19.44 MHz Oscillator On-Chip to Be Used with
External Crystal
Loss of Lock Indicator
Loopback Mode for High Speed Test Data
Output Squelch and Bypass Features
Single-Supply Operation: 3.3 V
Low Power: 540 mW Typical
7 mm ؋ 7 mm 48-Lead LFCSP
APPLICATIONS
SONET OC-48, SDH STM-16, and 15/14 FEC
WDM Transponders
Regenerators/Repeaters
Test Equipment
Backplane Applications
PRODUCT DESCRIPTION
The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for –40؇C to +85؇C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gb/s and 2.66 Gb/s
digital wrapper rate is supported by the ADN2811, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at
the output.
The ADN2811 is available in a compact 7 mm × 7 mm 48-lead
chip scale package.
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC VEE
2 ADN2811
PIN
QUANTIZER
NIN
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
CF1 CF2
LOL
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
VREF
LEVEL
DETECT
THRADJ SDOUT
DATA
RETIMING
2
DATAOUTP/N
2
CLKOUTP/N
FRACTIONAL
DIVIDER
RATE
2
2
/n
XTAL
OSC
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION
ADN2811
www.DataSheet4U.com
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
PIN 1
INDICATOR
ADN2811
TOP VIEW
NC = NO CONNECT
36 VCC
35 VCC
34 VEE
33 VEE
32 NC
31 NC
30 RATE
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
PIN FUNCTION DESCRIPTION
Pin No.
1
2, 26, 28, Pad
3, 9, 16, 19, 22, 27, 29,
33, 34, 42, 43, 46
4
5
6
7
8
10
11
12
13
Mnemonic
THRADJ
VCC
VEE
VREF
PIN
NIN
SLICEP
SLICEN
LOL
XO1
XO2
REFCLKN
14 REFCLKP
15 REFSEL
17
18
20, 47
21
23
24
25
30
31, 32
35, 36
37
38
39
40
41
44
45
48
TDINP
TDINN
VCC
CF1
REFSEL1
REFSEL0
CF2
RATE
NC
VCC
DATAOUTN
DATAOUTP
SQUELCH
CLKOUTN
CLKOUTP
BYPASS
SDOUT
LOOPEN
Type
AI
P
P
AO
AI
AI
AI
AI
DO
AO
AO
DI
DI
DI
AI
AI
P
AO
DI
DI
AO
DI
DI
P
DO
DO
DI
DO
DO
DI
DO
DI
Description
LOS Threshold Setting Resistor
Analog Supply
Ground
Internal VREF Voltage. Decouple to GND with 0.1 µF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input
Differential Slice Level Adjust Input
Loss of Lock Indicator. LVTTL active high.
Crystal Oscillator
Crystal Oscillator
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS
(LVPECL, LVDS only at 155.52 MHz).
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS
(LVPECL, LVDS only at 155.52 MHz).
Reference Source Select. “0” = on-chip oscillator with external crystal;
“1” = external clock source, LVTTL.
Differential Test Data Input
Differential Test Data Input
Digital Supply
Frequency Loop Capacitor
Reference Frequency Select (See Table II) LVTTL.
Reference Frequency Select (See Table II) LVTTL.
Frequency Loop Capacitor
Data Rate Select (See Table I) LVTTL.
No Connect
Output Driver Supply
Differential Retimed Data Output. CML.
Differential Retimed Data Output. CML.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Bypass CDR Mode. Active high. LVTTL.
Loss of Signal Detect Output. Active high. LVTTL.
Enable Test Data Inputs. Active high. LVTTL.
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
REV. A
–5–
5 Page 
ADN2811
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table III.
Table II. Reference Frequency Selection
REFSEL
1
1
1
1
0
www.DataSheet4U.com
Applied Reference
REFSEL[1..0] Frequency (MHz)
00 19.44
01 38.88
10 77.76
11 155.52
XX REFCLKP/N Inactive. Use
19.44 MHz XTAL oscillator
on Pins XO1, XO2 (Pull
REFCLKP to VCC).
Table III. Required Crystal Specifications
Parameter
Value
Mode
Frequency/Overall Stability
Frequency Accuracy
Temperature Stability
Aging
ESR
Series Resonant
19.44 MHz ± 100 ppm
± 100 ppm
± 100 ppm
± 100 ppm
20 Ω max
Recommended Manufacturer:
Raltron (305) 593-6033
Part Number: H10S-19.440-S-EXT
REFSEL must be tied to VCC when the REFCLKN/P inputs
are active or tied to VEE when the oscillator is used. No
connection between the XO pin and REFCLK input is necessary
(see Figures 12–14). Note that the crystal should operate in series
resonant mode, which renders it insensitive to external parasitics.
No trimming capacitors are required.
Lock Detector Operation
The lock detector monitors the frequency difference between
the VCO and the reference clock and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency
(see Figure 15). This enables the phase loop, which pulls the
VCO frequency in the remaining amount and also acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss of lock signal is reasserted and con-
trol returns to the frequency loop, which will reacquire and
maintain a stable clock signal at the output.
LOL
1
1000
500
0
500 1000
Figure 15. Transfer Function of LOL
fVCO ERROR
(ppm)
The frequency loop requires a single external capacitor between
CF1 and CF2. The capacitor specification is given in Table IV.
Table IV. Recommended CF Capacitor Specification
Parameter
Value
Temperature Range
Capacitance
Leakage
Rating
–40؇C to +85؇C
>3.0 µF
<80 nA
>6.3 V
Recommended Manufacturer:
Murata Electronics (770) 436-1300
Part Number: GRM32RR71C475LC01
Squelch Mode
When the squelch input is driven to a TTL high state, both the
clock and data outputs are set to the zero state to suppress
downstream processing. If desired, this pin can be directly
driven by the LOS detector output, SDOUT. If the squelch func-
tion is not required, the pin should be tied to VEE.
Test Modes: Bypass and Loopback
When the bypass input is driven to a TTL high state, the
quantizer output is connected directly to the buffers driving the data
out pins, thus bypassing the clock recovery circuit (see Figure 16).
This feature can help the system to deal with nonstandard bit rates.
The Loopback Mode can be invoked by driving the LOOPEN
Pin to a TTL high state, which facilitates system diagnostic test-
ing. This will connect the test inputs (TDINP/N) to the clock
and data recovery circuit (per Figure 16). The test inputs have
internal 50 Ω terminations and can be left floating when not in
use. TDINP/N are CML inputs and can only be dc-coupled
when being driven by CML outputs. The TDINP/N inputs must
be ac-coupled if being driven by anything other than CML out-
puts. Bypass and loopback modes are mutually exclusive. Only
one of these modes can be used at any given time. The
ADN2811 will be put into an indeterminate state if both
BYPASS and LOOPEN pins are set to Logic 1 at the same time.
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADN2811.PDF ] | |
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