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WCSS0418V1P Schematic ( PDF Datasheet ) - Weida Semiconductor

Teilenummer WCSS0418V1P
Beschreibung 256K x 18 Synchronous-Pipelined Cache RAM
Hersteller Weida Semiconductor
Logo Weida Semiconductor Logo 




Gesamt 17 Seiten
WCSS0418V1P Datasheet, Funktion
Y7C1327
WCSS0418V1P
256K x 18 Synchronous-Pipelined Cache RAM
Features
• Supports 100-MHz bus for Pentiumand PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 256K by 18 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
www.DataSheet4U.com
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The WCSS0418V1P is a 3.3V, 256K by 18 synchronous-pipe-
lined cache SRAM designed to support zero wait state sec-
ondary cache with minimal glue logic.
The WCSS0418V1P I/O pins can operate at either the 2.5V or
the 3.3V level. The I/O pins are 3.3V tolerant when VD-
DQ=2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The WCSS0418V1P supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the four Byte Write
Select (BW[1:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[17:0]
GW
BWE
BW 1
BW0
18
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
CE
D
REGISTER
16
D DQ[15:8], DP[1] Q
BYTEWRITE
REGISTERS
D DQ[7:0], DP[0] Q
BYTEWRITE
REGISTERS
16
18
256KX18
MEMORY
ARRAY
CE1
CE2
CE3
OE
ZZ
D
CE
ENABLE CE
REGISTER
Q
D ENABLE DELAY Q
REGISTER
SLEEP
CONTROL
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Document #: 38-05247
18 18
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
DQ[15:0]
DP[1:0]
Revised February 6, 2001






WCSS0418V1P Datasheet, Funktion
WCSS0418V1P
Cycle Descriptions[1, 2, 3]
Next Cycle
Unselected
Add. Used
None
ZZ
L
CE3 CE2 CE1 ADSP ADSC ADV OE
XX1
X
0 XX
Unselected
None
L 1X0 0 X XX
Unselected
None
LX0 0 0 X XX
Unselected
None
L 1X0
1
0 XX
Unselected
None
LX00
1
0 XX
Begin Read
External
L010
0
X XX
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Continue Read
External
Next
L010
L XXX
1
1
0 XX
1 01
Continue Read Next
L XXX
1
1 00
Continue Read Next
LXX1
X
1 01
Continue Read Next
LXX1
X
1 00
Suspend Read Current
L XXX
1
1 11
Suspend Read Current
L XXX
1
1 10
Suspend Read Current
LXX1
X
1 11
Suspend Read Current
LXX1
X
1 10
Begin Write
Current
L XXX
1
1 1X
Begin Write
Current
LXX1
X
1 1X
Begin Write
External
L010
1
0 XX
Continue Write Next
L XXX
1
1 0X
Continue Write Next
LXX1
X
1 0X
Suspend Write Current
L XXX
1
1 1X
Suspend Write Current
LXX1
X
1 1X
ZZ “Sleep”
None
HXXX
X
X XX
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW[1:0], and GW. See Write Cycle Description table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Document #: 38-05247
Page 6 of 17

6 Page









WCSS0418V1P pdf, datenblatt
Switching Waveforms (continued)
Read/Write Cycle Timing[14, 15, 16, 17]
WCSS0418V1P
CLK
tADS
ADSP
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ADSC
ADV
Single Read
tCYC
Single Write
tCH
tADH
tADS
tADVS
tCL
tADH
Burst Read
Unselected
Pipelined Read
ADSP ignored with CE1 inactive
tAS
ADD
RD1
tADVH
WD2
tAH
GW
tWS
tWH
WE
CE1
tCES
tCEH
RD3
tWS
tWH CE1 masks ADSP
CE2
tCES
CE3
tCES
OE
tCEH
tCEH
tEOV
tEOHZ
Data In/Out
tEOLZ
tCO
1O1aaut
2a
In
See Note 17
tDS tDH
2a 3a
Out Out
3b
Out
= DON’T CARE = UNDEFINED
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
tDOH
3c 3d
Out Out
tCHZ
Document #: 38-05247
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