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PDF DFPIC1655X Data sheet ( Hoja de datos )
| Número de pieza | DFPIC1655X | |
| Descripción | High Performance Configurable 8-bit RISC Microcontroller | |
| Fabricantes | Digital Core Design | |
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DFPIC1655X
www.DataSheet4U.com High Performance Configurable
8-bit RISC Microcontroller
ver 2.02
OVERVIEW
The DFPIC1655X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core, dedi-
cated for operation with fast memory (typi-
cally on-chip). The core has been designed
with a special concern about low power con-
sumption.
The DFPIC1655X is software compatible
with the industry standard PIC16C554 and
PIC16C558. It employs a modified RISC
architecture (2 times faster than original
implementation).
The DFPIC1655X have enhanced core
features, configurable hardware stack, and
multiple internal and external interrupt
sources. The separate instruction and data
buses allow a 14 bit wide instruction word with
the separate 8 -bit wide data. The
DFPIC1655X typically achieve a 2:1 code
compression and a 8:1 speed improvement
over other 8-bit microcontrollers in their class.
The power-down mode SLEEP allow user
to reduce power consumption. User can wake
up the controller from SLEEP through several
external and internal interrupt and reset. An
integrated Watchdog Timer with it's own clock
signal provides protection against software
lock-up.
The DFPIC1655X Microcontroller fits
perfectly in applications ranging from high-
speed automotive and appliance motor control
All trademarks mentioned in this document
are trademarks of their respective owners.
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode and small used area
in programmable devices make this IP perfect
for applications applications with space and
power consumption limitations.
DFPIC1655X is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each
stage of SoC design flow
CPU FEATURES
● Software compatible with industry standard
PIC16C55X
● Harvard architecture 2 times faster com-
pared to original implementation
● 35 instructions
● 14 bit wide instruction word
● Up to 512 bytes of internal Data Memory
● Up to 64K bytes of Program Memory
● Configurable hardware stack
● Power saving SLEEP mode
● Fully synthesizable, static synchronous
design with no internal tri-states
● Scan test ready
● Technology independent HDL Source
Code
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
1 page  
I/O Ports – Block contains DFPIC1655X’s
general purpose I/O ports and data direction
registers (TRIS). The DFPIC1655X has two 8-
bit full bi-directional ports PORT A, PORT B.
Read and write accesses to the I/O port are
performed via their corresponding SFR’s
PORTA, PORTB. The reading instruction al-
ways reads the status of Port pins. Writing
instructions always write into the Port latches.
Each port’s pin has an corresponding bit in
TRISA and TRISB registers. When the bit of
TRIS register is set this means that the corre-
sponding bit of port is configured as an input
www.DataShe(aeotn4ucUte.pc)ou.mt drivers are set into the High Imped-
DoCD™ Debug Unit – it’s a real-time hard-
ware debugger provides debugging capability
of a whole SoC system. In contrast to other
on-chip debuggers DoCD™ provides non-
intrusive debugging of running application. It
can halt, run, step into or skip an instruction,
read/write any contents of microcontroller in-
cluding all registers, internal, external, pro-
gram memories, all SFRs including user de-
fined peripherals. Hardware breakpoints can
be set and controlled on program memory,
internal and external data memories, as well
as on SFRs. Hardware breakpoint is executed
if any write/read occurred at particular address
with certain data pattern or without pattern.
The DoCD™ system includes three-wire inter-
face and complete set of tools to communi-
cate and work with core in real time debug-
ging. It is built as scalable unit and some fea-
tures can be turned off to save silicon and
reduce power consumption. A special care on
power consumption has been taken, and
when debugger is not used it is automatically
switched in power save mode. Finally whole
debugger is turned off when debug option is
no longer used.
OPTIONAL MODULES
There are also available an optional pe-
ripherals, not included in presented
DFPIC1655X Microcontroller Core. The op-
tional peripherals, can be implemented in mi-
crocontroller core upon customer request.
● Full duplex UART
● SPI – Master and Slave Serial Peripheral
Interface
● PWM – Pulse Width Modulation Timer
● I2C bus controller – Master / Slave
PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
CYCLONE
CYCLONE II
STRATIX
STRATIX II
STRATIX GX
APEX II
APEX20KC
APEX20KE
APEX20K
ACEX1K
FLEX10KE
Speed
grade
-6
-6
-5
-3
-5
-7
-7
-1
-1
-1
-1
Logic Cells
660
663
661
591
661
804
739
739
739
804
804
Fmax
99 MHz
91 MHz
106 MHz
122 MHz
101 MHz
71 MHz
61 MHz
56 MHz
50 MHz
39 MHz
38 MHz
Core performance in ALTERA® devices
IMPROVEMENT
Most instruction of DFPIC1655X is exe-
cuted within 2 CLK cycles. Except the condi-
tional program memory branches in case that
the condition of branch instruction is met. The
table below shows sample instructions execu-
tion times:
Mnemonic DFPIC1655X PIC16C554
operands (CLK cycles) (CLK cycles)
ADDWF
2
4
ANDWF
2
4
RLF 2 4
BCF
24
DECFSZ
2(4)1
4(8)1
INCFSZ
BTFSC
2(4)1
2(4)1
4(8)1
4(8)1
BTFSS
2(4)1
4(8)1
CALL 2 8
GOTO
2
8
RETFIE
2
8
RETLW
2
8
RETURN
2
8
1 number of clock in case that result of
operation is 0.
Impr.
2
2
2
2
2
2
2
2
4
4
4
4
4
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
5 Page | ||
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