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PDF PLL1705 Data sheet ( Hoja de datos )
| Número de pieza | PLL1705 | |
| Descripción | (PLL1705 / PLL1706) 3.3-V DUAL PLL MULTICLOCK GENERATOR | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL1705 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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PLL1705
PLL1706
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
3.3-V DUAL PLL MULTICLOCK GENERATOR
FEATURES
D 27-MHz Master Clock Input
D Generated Audio System Clock:
– SCKO0: 768 fS (fS = 44.1 kHz)
www.DataSheet4U.com – SCKO1: 384 fS, 768 fS (fS = 44.1 kHz)
– SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,
96 kHz)
– SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2,
96 kHz)
D Zero PPM Error Output Clocks
D Low Clock Jitter: 50 ps (Typical)
D Multiple Sampling Frequencies:
– fS = 32, 44.1, 48, 64, 88.2, 96 kHz
D 3.3-V Single Power Supply
D PLL1705: Parallel Control
PLL1706: Serial Control
D Package: 20-Pin SSOP (150 mil), Lead-Free
Product
FUNCTIONAL BLOCK DIAGRAM
(ML) (MC) (MD)
SR FS2 FS1
APPLICATIONS
D DVD Players
D DVD Add-On Cards for Multimedia PCs
D Digital HDTV Systems
D Set-Top Boxes
DESCRIPTION
The PLL1705† and PLL1706† are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1705 and
PLL1706 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1705 can be controlled by sampling frequency-control
pins and those of the PLL1706 can be controlled through
serial-mode control pins. The device gives customers both
cost and space savings by eliminating external
components and enables customers to achieve the very
low-jitter performance needed for high performance audio
DACs and/or ADCs. The PLL1705 and PLL1706 are ideal
for MPEG-2 applications which use a 27-MHz master
clock such as DVD players, DVD add-on cards for
multimedia PCs, digital HDTV systems, and set-top
boxes.
CSEL
VCC AGND VDD1–3 DGND1–3
Reset
XT1
OSC
XT2
Mode Control Interface
Power Supply
PLL2
PLL1
Divider
Divider
Divider
( ): PLL1706
MCKO1 MCKO2
SCKO0 SCKO1
SCKO2
SCKO3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
1 page  
www.ti.com
PLL1705
PLL1706
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
CSEL
9 – Analog ground
12 IN SCKO1 frequency selection control(1)
DGND1 4 – Digital ground 1
DGND2 16 – Digital ground 2
DGND3
FS1(MD)
FS2(MC)
17
5
6
– Digital ground 3
IN Sampling frequency group control in PLL1705, data input for serial control in PLL1706(1)
IN Sampling frequency group control in PLL1705, bit clock input for serial control in PLL1706(1)
www.DataSheet4U.McoCmKO1
14 OUT 27-MHz master clock output 1
MCKO2
15 OUT 27-MHz master clock output 2
SCKO0
19 OUT System clock output 0 (33.8688 MHz fixed)
SCKO1
18 OUT System clock output 1 (selectable for 44.1 kHz)
SCKO2
SCKO3
SR(ML)
2 OUT System clock output 2 (256 fS)
3 OUT System clock output 3 (384 fS)
7 IN Sampling rate control in PLL1705, load strobe input for serial control in PLL1706(1)
VCC
VDD1
VDD2
VDD3
XT1
8 – Analog power supply, 3.3 V
1 – Digital power supply 1, 3.3 V
13 – Digital power supply 2, 3.3 V
20 – Digital power supply 3, 3.3 V
10 IN 27-MHz crystal oscillator, or external clock input
XT2 11 OUT 27-MHz crystal oscillator, must be OPEN for external clock input mode
(1) Schmitt-trigger input with internal pulldown.
5
5 Page 
www.ti.com
PLL1705
PLL1706
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
FUNCTION CONTROL
The built-in functions of the PLL1705 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1
(pin 5) and FS2 (pin 6). The PLL1706 can be controlled in the serial mode (software mode), which uses a three-wire
interface by ML (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.
Table 4. Selectable Functions
SELECTABLE FUNCTION
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
Sampling rate select (standard/double)
Each clock output enable/disable
Power down
www.DataSheet4U.com
PLL1705 (Parallel Mode)
In the parallel mode, the following functions can be selected:
Sampling Frequency Group Select
PARALLEL MODE
Yes
Yes
No
No
The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).
FS2 (PIN 6)
LOW
LOW
HIGH
HIGH
FS1 (PIN 5)
LOW
HIGH
LOW
HIGH
SAMPLING FREQUENCY
48 kHz
44.1 kHz
32 kHz
Reserved
SERIAL MODE
Yes
Yes
Yes
Yes
Sampling Rate Select
The sampling rate can be selected by SR (pin 7)
SR (PIN 7)
LOW
HIGH
SAMPLING RATE
Standard
Double
PLL1706 (Serial Mode)
The built-in functions of the PLL1706 are shown in Table 5. These functions are controlled using the ML, MC, and MD serial
control signals.
Table 5. Selectable Functions
SELECTABLE FUNCTION
Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz)
Sampling rate select (standard/double)
Each clock output enable/disable
Power down
DEFAULT
48-kHz group
Standard
Enabled
Disabled
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet PLL1705.PDF ] | |
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