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PDF PLL103-07 Data sheet ( Hoja de datos )
| Número de pieza | PLL103-07 | |
| Descripción | 2 DIMM DDR Fanout Buffer | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL103-07 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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FEATURES
• Generates 12-output buffers from one input.
• Supports VIA Pro266 DDR chipset.
• Supports up to 2 DDR DIMMS.
• Supports up to 400MHz DDR, SDRAMS.
• One additional output for feedback.
• 6 differential clock distribution.
• Less than 5ns delay.
www.DataShee•t4U.Scokmew between any outputs is less than 100 ps.
• 2.5V Supply range.
• Available in 28-pin SSOP.
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
BUF_IN
DDR0T
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
DDR4C
DDR5T
DDR5C
FBOUT
Preliminary PLL103-07
2 DIMM DDR Fanout Buffer
PIN CONFIGURATION
FBOUT
GND
DDRT0
DDRC0
VDD2.5
GND
DDRT1
DDRC1
VDD2.5
BUF_IN
GND
DDRT2
DDRC2
VDD2.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note: #: Active Low
28 GND
27 DDRT5
26 DDRC5
25 VDD2.5
24 GND
23 DDRT4
22 DDRC4
21 VDD2.5
20 GND
19 DDRT3
18 DDRC3
17 VDD2.5
16 SCLK
15 SDATA
DESCRIPTIONS
The PLL103-07 is designed as a 2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 12 outputs. These outputs can be
configured to support 2 DDR DIMMs. The PLL103-07
can be used in conjunction with the PLL202-04 or
similar clock synthesizer for the VIA Pro 266 chipset.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 1
1 page  
Preliminary PLL103-07
2 DIMM DDR Fanout Buffer
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
www.DataSheOetu4tUpu.ctoVmoltage, dc
Storage Temperature
Ambient Operating Temperature
ESD Voltage
VDD VSS-0.5 7.0
V
VI
VSS-0.5
VDD+0.5
V
VO
VSS-0.5
VDD+0.5
V
TS -65 150 °C
TA 0 70 °C
2 KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Operating Conditions
Supply Voltage
Input Capacitance
Output Capacitance
PARAMETERS
SYMBOL
VDD2.5
CIN
COUT
MIN.
2.375
MAX.
2.625
5
6
UNITS
V
pF
pF
3. Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High
Voltage
Output Low
Voltage
Output High
Current
Output Low
Current
VIH All Inputs except I2C
VIL All inputs except I2C
IIH VIN = VDD
IIL VIN = 0
VOH IOL = -12mA,
VDD = 2.375V
VOL IOL = 12mA,
VDD = 2.375V
IOH VDD = 2.375V, VOUT=1V
IOL VDD = 2.375V, VOUT=1.2V
Note: TBM: To be measured
MIN.
2.0
VSS-0.3
1.7
TYP.
MAX.
VDD+0.3
0.8
TBM
TBM
UNITS
V
V
uA
uA
V
0.6 V
-18 -32
mA
26 35
mA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PLL103-07.PDF ] | |
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