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EL5372 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer EL5372
Beschreibung (EL5172 / EL5372) 250MHz Differential Line Receivers
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 16 Seiten
EL5372 Datasheet, Funktion
®
Data Sheet
EL5172, EL5372
January 25, 2008
FN7311.8
250MHz Differential Line Receivers
The EL5172 and EL5372 are single and triple high
bandwidth amplifiers designed to extract the difference
signal from noisy environments. They are primarily targeted
for applications such as receiving signals from twisted-pair
lines or any application where common mode noise injection
is likely to occur.
The EL5172 and EL5372 are stable for a gain of one and
www.DataShereetq4uUir.ceosmtwo external resistors to set the voltage gain.
The output common mode level is set by the reference pin
(VREF), which has a -3dB bandwidth of over 120MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
The output can deliver a maximum of ±60mA and is short
circuit protected to withstand a temporary overload
condition.
The EL5172 is available in the 8 Ld SOIC and 8 Ld MSOP
packages and the EL5372 in a 24 Ld QSOP package. Both
are specified for operation over the full -40°C to +85°C
temperature range.
Pinouts
EL5172
(8 LD SOIC, MSOP)
TOP VIEW
EL5372
(24 LD QSOP)
TOP VIEW
FB 1
IN+ 2
IN- 3
REF 4
+
-
8 OUT REF1 1
7 VS-
INP1 2
6 VS+ INN1 3
5 EN
NC 4
REF2 5
INP2 6
INN2 7
NC 8
REF3 9
INP3 10
INN3 11
NC 12
+
-
+
-
+
-
24 NC
23 FB1
22 OUT1
21 NC
20 VSP
19 VSN
18 NC
17 FB2
16 OUT2
15 EN
14 FB3
13 OUT3
Features
• Differential input range ±2.3V
• 250MHz 3dB bandwidth
• 800V/µs slew rate
• 60mA maximum output current
• Single 5V or dual ±5V supplies
• Low power - 5mA to 6mA per channel
• Pb-free available (RoHS compliant)
Applications
• Twisted-pair receivers
• Differential line receivers
• VGA over twisted-pair
• ADSL/HDSL receivers
• Differential to single-ended amplification
• Reception of analog signals in a noisy environment
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2005, 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.






EL5372 Datasheet, Funktion
Connection Diagrams
INP
INN
REF
RS2
50Ω
RS2
50Ω
RS3
50Ω
RG
RF = 0Ω
1 FB
OUT 8
2 INP
VSN 7
3 INN
VSP 6
4 REF
EN 5
EL5172
-5V
CL
2.7pF
VOUT
RL
500Ω
EN
+5V
REF1
INP1
INN1
REF2
INP2
INN2
REF3
INP3
INN3
RSP1 RSN1 RSR1 RSP2 RSN2 RSR2 RSP3 RSN3 RSR3
50Ω 50Ω 50Ω 50Ω 50Ω 50Ω 50Ω 50Ω 50Ω
RG
1 REF1
2 INP1
NC 24
FB1 23
RF
3 INN1 OUT1 22
4 NC
NC 21
5 REF2 VSP 20
6 INP2
7 INN2
8 NC
VSN 19
NC 18
FB2 17
RG
RF
9 REF3
10 INP3
11 INN3
OUT2 16
EN 15
FB3 14
RG
RF
12 NC
OUT3 13
EL5372
+5V
-5V
ENABLE
CL1
2.7pF
CL2
2.7pF
CL3
2.7pF
RL1
500Ω
OUT1
RL2
500Ω
OUT2
RL3
500Ω
OUT3

6 Page









EL5372 pdf, datenblatt
EL5172, EL5372
120µA for IS- typically, thereby effectively eliminating the
power consumption. The amplifier's power-down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to VS+ pin. Letting the
EN pin float or applying a signal that is less than 1.5V below
VS+ will enable the amplifier. The amplifier will be disabled
when the signal at EN pin is above VS+ - 0.5V. If a TTL
signal is used to control the enabled/disabled function,
Figure 24 could be used to convert the TTL signal to CMOS
signal.
5V
www.DataSheet4U.com
CMOS/TTL
10k
1k
EN
FIGURE 24.
Output Drive Capability
The EL5172 and EL5372 have internal short circuit
protection. Its typical short circuit current is ±95mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL5172 and
EL5372, it is possible to exceed the +135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to Equation 2:
PDMAX
=
T----J---M-----A----X-----–-----T----A---M-----A----X--
ΘJA
(EQ. 2)
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
Assuming the REF pin is tied to GND for VS = ±5V
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
For sourcing, use Equation 3:
PDMAX =
VS
×
ISMAX
+
(VS+
VOUT
)
×
--V-----O----U----T----
RLOAD
×i
(EQ. 3)
For sinking, use Equation 4:
PDMAX = [VS × ISMAX + (VOUT VS- ) × ILOAD ] × i
(EQ. 4)
Where:
• VS = Total supply voltage
• ISMAX = Maximum quiescent supply current per channel
• VOUT = Maximum output voltage of the application
• RLOAD = Load resistance
• ILOAD = Load current
• i = Number of channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
12 FN7311.8
January 25, 2008

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