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89C51RC Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer 89C51RC
Beschreibung AT89C51RC
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 36 Seiten
89C51RC Datasheet, Funktion
Features
Compatible with MCS®-51 Products
32K Bytes of Reprogrammable Flash Memory
Endurance: 1000 Write/Erase Cycles
4V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
512 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
www.DataShLeoetw4U-p.coowmer Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Hardware Watchdog Timer
Dual Data Pointer
Power-off Flag
Green (Pb/Halide-free) Packaging Option
1. Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read-only memory and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard 80C51 and 80C52 instruction set and
pinout. The on-chip Flash allows the program memory to be user programmed by a
conventional nonvolatile memory programmer. A total of 512 bytes of internal RAM
are available in the AT89C51RC. The 256-byte expanded internal RAM is accessed
via MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The
other 256-byte RAM segment is accessed the same way as the Atmel AT89-series
and other 8052-compatible products. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which pro-
vides a highly-flexible and cost-effective solution to many embedded control
applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con-
tinue functioning. The Power-down mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the next external interrupt or hardware
reset.
8-bit
Microcontroller
with 32K Bytes
Flash
AT89C51RC
1920C–MICRO–03/05






89C51RC Datasheet, Funktion
4.10 EA/VPP
4.11 XTAL1
www.Data4Sh.1ee2t4U.cXomTAL2
External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
5. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1.
Table 5-1. AT89C51RC SFR Map and Reset Values
0F8H
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
B
00000000
ACC
00000000
PSW
00000000
T2CON
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111
T2MOD
XXXXXX00
SBUF
XXXXXXXX
TMOD
00000000
SP
00000111
RCAP2L
00000000
AUXR1
XXXXXXX0
TL0
00000000
DP0L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
TL1
00000000
DP0H
00000000
TH0
00000000
DP1L
00000000
TH1
00000000
DP1H
00000000
WDTRST
XXXXXXXX
AUXR
XXX00X00
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
PCON
0XXX0000
8FH
87H
6 AT89C51RC
1920C–MICRO–03/05

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89C51RC pdf, datenblatt
9. Using the WDT
www.DataSheet4U.com
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches
8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every
machine cycle while the oscillator is running. This means the user must re-initialize the WDT at
least every 8191 machine cycles. To re-initialize the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.
When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed within the time required to
prevent a WDT reset.
10. WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89C51RC is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for
the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to
reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)
as the default state. To prevent the WDT from resetting the AT89C51RC while in IDLE mode,
the user should always set up a timer that will periodically exit IDLE, service the WDT, and reen-
ter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
11. UART
The UART in the AT89C51RC operates the same way as the UART in the AT89C51 and
AT89C52. For more detailed information on the UART operation, please click on the document
link below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
12 AT89C51RC
1920C–MICRO–03/05

12 Page





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