PDF PMB2402 Data sheet ( Hoja de datos )

Número de pieza	PMB2402
Descripción	GSM Receiver Circuit
Fabricantes	Siemens Semiconductor
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No Preview Available ! GSM Receiver Circuit PMB 2402 Preliminary Data Bipolar IC www.DataSheeFt4eU.acotumres q Heterodyne receiver with demodulator q Down mixing from 900 MHz receiver band to the base band q Demodulation and generation of I/Q-baseband components q Low mixer noise 10 dB (SSB) q Input high intercept point + 2 dB q Integrated 0˚ and 90˚ phase shifter q 82 dB AGC-range q On-chip second LO-oscillator with external tuning circuit q Two differential operational amplifiers q Low power consumption due to highly flexible power- down capability q Wide input frequency range up to 1 GHz q Wide IF-range from 35 MHz to 100 MHz q Wide output frequency range up to 13.5 MHz q P-DSO-28-4 shrink package q Temperature range – 25 ˚C to 85 ˚C P-DSO-28-4 Applications q Digital mobile cellular systems as GSM, DAMPS, JDC q Various demodulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK q Space and power saving optimizations of existing discrete demodulator circuits Type PMB 2402S PMB 2402S Version V 2.1 V 2.1 Ordering Code Q67000-A6072 Q67006-A6072 Package P-DSO-28-4 (Shrink, SMD)) P-DSO-28-4 (Shrink, SMD, Tape + Reel) Functional Description The PMB 2402 is a single-chip single-conversion heterodyn PM-receiver with phase shifting circuitry for the I/Q-phase baseband demodulation on chip. It also includes the second local oscillator, a gain controlled second IF-amplifier, two differential operational amplifiers for baseband filtering purposes and power down circuitry. The PMB 2402 is designed for digital mobile telephones according to the GSM-standard and other digital systems. Semiconductor Group 1 01.94 1 page PMB 2402 Circuit Description The input signal SI/SI and the amplified first local oscillator signal LO1/LO1 are mixed down to an intermediate frequency (IF). The open collector output of the mixer generates a differential current at pins MO/MO which is filtered by an external resonant circuit. The resulting voltage drives an external SAW-filter. The second local oscillator signal LO2 is generated in an on chip VCO and is fed to two dividers, which generate orthogonal signals at a quarter of VCO-frequency. The internal LO-signal is fed to www.DataSheeat4nU.caodmditionally divider, whose output signal LO2O is fed to the RF-signal of PLL-synthesizer. The filtered IF-signal reenters the chip at the IFI/IFI input, where it is amplified and demodulated to the final baseband output frequency with each of the orthogonal signals. The resulting in-phase and quadrature signals pass through differential output drivers and appear at SOI/SOI and SOQ/SOQ outputs, respectively. The amplification of the IF-signal before the second mixer stage is performed by a gain-controlled amplifier, the gain being determined by the voltage at the gain control input GC. Two differential operational amplifiers with the input signals INI/INI (INQ/INQ) and the output signals OUTI/OUTI (OUTQ/OUTQ) can be used as active filters. Differential signals and symmetrical circuitry are used throughout, except at the signal output. Bias drivers generate internal temperature- and supply voltage-compensated reference voltages required by various circuit blocks. Switching the power down inputs PD1 and PD2 from high to low (see table) sets the circuit from its normal operating mode into a mode with reduced supply current. PD1 PD2 RF-Part IF-Part VCO/Divders L L OFF OFF ON L H OFF ON ON H L ON OFF ON H H ON ON ON Semiconductor Group 5 5 Page PMB 2402 AC/DC-Characteristics (cont’d) Parameter Input capacitance Input level www.DataSheeIt4nUp.cuotmfrequency Symbol Limit Values Unit min. typ. max. CLO2 PLO2 VLO2 fLO2 0.7 1 – 20 63 140 1.3 pF 0 dBm 630 mVpp 400 MHz Test Condition into 50 Ω Test Circuit 2b 1.1 1.1 1.1 Voltage Controlled Oscillator VCO (LO2) VCO-frequency fVCO 120 250 MHz with ext. capacitors 1.2 VCO Output LO2O Output resistance RLO2O Output capacitance CLO2O Output level VLO2O Output frequency fLO2O 0.9 1.2 1.5 0.7 1 1.3 150 160 120 140 15 50 kΩ pF mVpp mVpp MHz IF ≤ 75 MHz IF ≥ 75 MHz 1 1 1 Signal Outputs SOI/SOI, SOQ/SOQ Output resistance RSO Output capacitance CSO SO frequency roll off fSO DC output level Diff. output offset voltage VSO VSO/SO Voltage gain from GSO IF to I/Q-output 175 250 325 Ω 0.7 1 1.3 pF 13.5 MHz 2.0 2.5 V 28 mV 57 61 65 dB – 25 – 21 – 17 dB see diagram 6 between I/I or Q/Q 1 1 VGC = 0 V VGC = 2 V see dia- 1 gram 2 + 3 Gain Control Input GC GC-input voltage VGC 0 2V GC-input current – IGC 1 µA 0 V ≤ VGC ≤ 2 V Gain control factor FGC 40 dB/V FGC = dGSO/dVGC see diagram 3 1 1 1 Semiconductor Group 11 11 Page

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