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PDF W3DG648V-D1 Data sheet ( Hoja de datos )
| Número de pieza | W3DG648V-D1 | |
| Descripción | SDRAM UNBUFFERED | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
W3DG648V-D1
64MB – 2x4Mx64 SDRAM, UNBUFFERED
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V ± 0.3V Power Supply
Dual Rank
144 pin SO-DIMM JEDEC
www.Data• SDh1e: e2t74.9U4.mcomm(1.10")
DESCRIPTION
The W3DG648V is a 2x4Mx64 synchronous DRAM module
which consists of eight 4Mx16 SDRAM components in
TSOP II package, and one 2Kb EEPROM in an 8 pin
TSSOP package for Serial Presence Detect which are
mounted on a 144 pin SO-DIMM multilayer FR4 Substrate.
This module is structured as 2 ranks of 8Mx64 SDRAM.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN BACK PIN BACK
1 VSS 2 VSS 49 DQ13 50 DQ45 97 DQ22 98 DQ54
3 DQ0 4 DQ32 51 DQ14 52 DQ46 99 DQ23 100 DQ55
5 DQ1 6 DQ33 53 DQ15 54 DQ47 101 VCC 102 VCC
7 DQ2 8 DQ34 55 VSS 56 VSS 103 A6 104 A7
9 DQ3 10 DQ35 57 NC 58 NC 105 A8 106 BA0
11 VCC 12 VCC 59 NC 60 NC 107 VSS 108 VSS
13 DQ4 14 DQ36 61 CLK0 62 CKE0 109 A9 110 BA1
15 DQ5 16 DQ37 63 VCC 64 VCC 111 A10/AP 112 A11
17 DQ6 18 DQ38 65 RAS# 66 CAS# 113 VCC 114 VCC
19 DQ7 20 DQ39 67 WE# 68 CKE1 115 DQMB2 116 DQMB6
21 VSS 22 VSS 69 CS0# 70 NC 117 DQMB3 118 DQMB7
23 DQMB0 24 DQMB4 71 CS1# 72 NC 119 VSS 120 VSS
25 DQMB1 26 DQMB5 73 NC 74 CLK1 121 DQ24 122 DQ56
27 VCC 28 VCC 75 VSS 76 VSS 123 DQ25 124 DQ57
29 A0 30 A3 77 NC 78 NC 125 DQ26 126 DQ58
31 A1 32 A4 79 NC 80 NC 127 DQ27 128 DQ59
33 A2 34 A5 81 VCC 82 VCC 129 VCC 130 VCC
35 VSS 36 VSS 83 DQ16 84 DQ48 131 DQ28 132 DQ60
37 DQ8 38 DQ40 85 DQ17 86 DQ49 133 DQ29 134 DQ61
39 DQ9 40 DQ41 87 DQ18 88 DQ50 135 DQ30 136 DQ62
41 DQ10 42 DQ42 89 DQ19 90 DQ51 137 DQ31 138 DQ63
43 DQ11 44 DQ43 91 VSS 92 VSS 139 VSS 140 VSS
45 VCC 46 VCC 93 DQ20 94 DQ52 141 SDA** 142 SCL**
47 DQ12 48 DQ44 95 DQ21 96 DQ53 143 VCC 144 VCC
PIN NAMES
A0 – A11
BA0-1
DQ0-63
CLK0, CLK1
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
DQMB0-7
VCC
VSS
SDA
SCL
DNU
NC
Address Input (Multiplexed)
Select Bank
Data Input/Output
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQMB
Power Supply (3.3V)
Ground
Serial Data I/O
Serial Clock
Do Not Use
No Connect
* These pins are not used in this module.
** These pins should be NC in the system which
does not support SPD.
July 2005
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3DG648V-D1
PACKAGE DIMENSIONS FOR D1
Ordering Information
Speed
CAS Latency
Height*
W3DG648V10D1
100MHz
CL=2
27.94 (1.100”)
W3DG648V7D1
133MHz
CL=2
27.94 (1.100”)
W3DG648V75D1
133MHz
CL=3
27.94 (1.100”)
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is
shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult
factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D1
www.DataSheet4U.com
2.01 (0.079 Min)
67.72
(2.661 Max)
4.32
(0.170)
MAX.
3.99
(0.157)
23.14
(0.913)
28.2
(1.112)
32.79
(1.291)
4.60 (0.181)
1.50 (0.059)
19.99
(0.787)
27.94
(1.100)
Max
* All Dimensions are in millimeters and (inches).
0.99 ± 0.10
(0.039)
(± 0.004)
July 2005
Rev. 6
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet W3DG648V-D1.PDF ] | |
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