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PDF DP80390CPU Data sheet ( Hoja de datos )
| Número de pieza | DP80390CPU | |
| Descripción | Pipelined High Performance 8-bit Microcontroller | |
| Fabricantes | Digital Core Design | |
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DP80390CPU
Pipelined High Performance
8-bit Microcontroller
ver 4.02
OVERVIEW
DP80390CPU is an ultra high perform-
ance, speed optimized soft core of a single-
chip 8-bit embedded controller dedicated for
operation with fast (typically on-chip) and slow
(off-chip) memories. It supports up to 8 MB of
linear code and 16 MB of linear data spaces.
The core has been designed with a special
concern about performance to power con-
sumption ratio. This ratio is extended by an
advanced power management unit PMU.
DP80390CPU soft core is 100% binary-
compatible with the industry standard 80390 &
8051 8-bit microcontroller. There are two con-
figurations of DP80390CPU: Harward where
internal data and program buses are sepa-
rated, and von Neumann with common pro-
gram and external data bus. DP80390CPU has
Pipelined RISC architecture 10 times faster
compared to standard architecture and exe-
cutes 85-200 million instructions per second.
This performance can also be exploited to
great advantage in low power applications
where the core can be clocked over ten times
more slowly than the original implementation
for no performance penalty.
DP80390CPU is delivered with fully
automated testbench and complete set of
tests allowing easy package validation at each
stage of SoC design flow.
CPU FEATURES
● 100% software compatible with industry
standard 80390 & 8051
○ LARGE mode – 8051 instruction set
○ FLAT mode – 80390 instruction set
● Pipelined RISC architecture enables to
execute instructions 10 times faster com-
pared to standard 8051
● 24 times faster multiplication
● 12 times faster addition
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 8M bytes of linear Program Memory
○ 64 kB of internal (on-chip) Program Memory
○ 8 MB external (off-chip) Program Memory
● Up to 16M bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
● De-multiplexed Address/Data bus to allow
easy connection to memory
● Dedicated signal for Program Memory
writes.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
1 page  
PIN TYPE
DESCRIPTION
rsto output Reset output
port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
port3o[7:0]
output Port 3 output
prgaddr[15:0] output Internal program memory address bus
prgdatao[7:0] output Data bus for internal program memory
prgramwr
output Internal program memory write
sxdmaddr[15:0] output Sync XDATA memory address bus
(SXDM)
sxdmdatao[7:0]
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sxdmoe
output Data bus for Sync XDATA memory
(SXDM)
output Sync XDATA memory read (SXDM)
sxdmwe
output Sync XDATA memory write (SXDM)
xaddr[23:0]
output Address bus for external memories
xdatao[7:0]
output Data bus for external memories
xdataz
output Turn xdata bus into ‘Z’ state
xprgrd
output External program memory read
xprgwr
output External program memory write
xdatard
output External data memory read
xdatawr
output External data memory write
ramaddr[7:0]
output Internal Data Memory address bus
ramdatao[7:0] output Data bus for internal data memory
ramoe
output Internal data memory output enable
ramwe
output Internal data memory write enable
sfraddr[6:0]
output Address bus for user SFR’s
sfrdatao[7:0]
output Data bus for user SFR’s
sfroe
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo output DoCD™ TAP data output
rtck output DoCD™ return clock line
debugacs
output DoCD™ accessing data
coderun
output CPU is executing an instruction
pmm
output Power management mode indicator
stop output Stop mode indicator
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
All trademarks mentioned in this document
are trademarks of their respective owners.
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains mem-
ory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It per-
forms the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
Synchronous eXternal Data Memory
(SXDM) Interface – contains XDATA memory
access related logic allowing fast access to
synchronous memory devices. It performs the
external Data Memory addressing and data
transfers. This memory can be used to store
large variables frequently accessed by CPU,
improving overall performance of application.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Man-
agement Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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