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PDF DP80C51 Data sheet ( Hoja de datos )
| Número de pieza | DP80C51 | |
| Descripción | Pipelined High Performance 8-bit Microcontroller | |
| Fabricantes | Digital Core Design | |
| Logotipo |  |
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DP80C51
Pipelined High Performance
8-bit Microcontroller
ver 4.01
OVERVIEW
DP80C51 is an ultra high performance,
speed optimized soft core of a single-chip 8-
bit embedded controller dedicated for opera-
tion with fast (typically on-chip) and slow (off-
chip) memories. The core has been designed
with a special concern for performance to
power consumption ratio. This ratio is ex-
tended by an advanced power management
unit PMU.
DP80C51 soft core is 100% binary and
pin compatible with the industry standard
8051 8-bit microcontroller. There are two con-
figurations of the DP80C51: Harward, where
external data and program buses are sepa-
rated, and von Neumann, with common pro-
gram and external data bus. DP80C51 has
Pipelined RISC architecture up to 10 times
faster compared to standard architecture and
executes 85-200 million instructions per
second. This performance can also be ex-
ploited to great advantage in low power appli-
cations where the core can be clocked over ten
times more slower than the original implemen-
tation for no performance penalty.
DP80C51 is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each stage
of SoC design flow.
CPU FEATURES
● 100% pin compatible with industry standard
8051
● 100% software compatible with industry
standard 8051
● Pipelined RISC architecture enables to
execute instructions up to 10 times faster
compared to standard 8051
● 24 times faster multiplication
● 12 times faster addition
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
● Up to 64K bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
● Dedicated signal for Program Memory
writes.
● Interface for additional Special Function
Registers
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
1 page  
BLOCK DIAGRAM
prgramdatai(7:0)
prgromdatai(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
Opcode
decoder
Program
memory
interface
I/O Port
registers
Timers
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
ea
ale
psen
www.DataSheet4U.com pswr
External
memory
interface
UART
Interrupt
controller
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
clk
reset
rsto
Control
Unit
Internal
data
memory
interface
User SFR’s
interface
Power
Manage-
ment Unit
DoCD™
Debug Unit
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
ALU
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
All trademarks mentioned in this document
are trademarks of their respective owners.
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains mem-
ory access related registers such as Data
Page High (DPH), Data Page Low (DPL). It
performs the external Program and Data
Memory addressing and data transfers. Pro-
gram fetch cycle length can be programmed by
user. This feature is called Program Memory
Wait States, and allows core to work with dif-
ferent speed program memories.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers. Note that external pins of
this module are connected to appropriate pins
of P3 port.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK peri-
ods when appropriate timer is enabled. In the
counter mode the timer registers are incre-
mented every falling transition on their corre-
sponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock sources for UARTs. Note that external
pins of this module are connected to appropri-
ate pins of P3 port.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) regis-
ters. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
5 Page | ||
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| PDF Descargar | [ Datasheet DP80C51.PDF ] | |
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