PDF CY7C9235A Data sheet ( Hoja de datos )

Número de pieza	CY7C9235A
Descripción	SMPTE-259M/DVB-ASI Scrambler/Controller
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C9235A Features • Fully compatible with SMPTE-259M • Fully compatible with DVB-ASI • Operates from a single +5V supply • 44-pin PLCC package • Encodes both 8- and 10-bit parallel digital streams for 27M characters/sec (270 Mbits/sec serial) • Operates with CY7B9234 SMPTE HOTLink serializer/transmitter • ×9 + ×4 + 1 scrambler and NRZI encoder may be bypassed for raw data output www.DataSheet4U.com Functional Description SMPTE-259M Operation The CY7C9235A is a CMOS integrated circuit designed to encode SMPTE-125M bit-parallel digital characters (or other data formats) using the SMPTE-259M encoding rules. Following encoding, the characters are output as bit-parallel characters ready for serialization. The encoded outputs of the CY7C9235A are designed to be directly mated to a CY7B9234 HOTLink transmitter, which then converts the bit-parallel characters into a SMPTE-259M compatible high-speed serial data stream. SMPTE-259M/DVB-ASI Scrambler/Controller This device performs both TRS (sync) detection and filtering, data scrambling with the SMPTE-259M ×9 + ×4 + 1 algorithm, and NRZ-to-NRZI encoding. These functions operate at a 27 MHz character rate. For those systems operating with non-SMPTE-259M compliant video streams (or for diagnostic purposes), the scrambler and NRZI encoding functions can be disabled. DVB-ASI Operation The CY7C9235A also contains the necessary multiplexers, control inputs, and outputs, to sequence out a DVB-ASI compliant video stream. DVB-ASI operation is enabled through activation of a single input signal. This allows a single serial output port to support both SMPTE and DVB data streams under software or hardware control. In DVB-ASI mode the CY7C9235A operates with two enable signals (ENA and ENN) to allow data to be presented from either synchronous (clocked) or asynchronous FIFOs. When data is not available, the CY7C9235A ensures that the proper fill character (K28.5) is generated by the attached CY7B9234 serializer. The CY7C9235A operates from a single +5V supply. It is available in a 44-pin PLCC space saving package. Logic Block Diagram PD9(SVS) PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0(SC/D) TRS_FILT SC/D_EN SVS_EN BYPASS DVB_EN ENA ENN CKW OE 10 10 10 10 10 TRS_DET Q9(SVS) Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0(SC/D) ENA_OUT Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-02082 Rev. Revised October 13, 2003 1 page CY7C9235A Maximum Ratings[1] (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ..................................... −40°C to +125°C Supply Voltage to Ground Potential .................−0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State .....................................................−0.5V to +7.0V Output Current into Outputs .........................................16 mA DC Input Voltage ................................................. −0.5V to +7.0V Static Discharge Voltage ...............................................> 2001 V (per MIL-STD-883, Method 3015) DC Input Current .............................................................± 20 mA Latch-up Current ...........................................................> 200 mA Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC 5V ± 5% Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage www.DataShVeILet4U.comInput LOW Voltage IIX Input Load Current IOZ Output Leakage Current IOS Output Short Circuit Current[3,4] Test Conditions VCC=Min., IOH = −3.2 mA VCC=Min., IOL = 16.0 mA Guaranteed Input Logical HIGH Voltage for all Inputs[2] Guaranteed Input Logical LOW Voltage for all Inputs[2] VI = VCC or VSS VO = VCC or VSS VCC = Max., VOUT = 0.5V Capacitance[4] Parameter CIN COUT CCLK Description Input Capacitance Output Capacitance Clock Signal Capacitance Test Conditions VIN = 5.0V at f = 1 MHz VIN = 5.0V at f = 1 MHz VIN = 5.0V at f = 1 MHz Min. 2.4 2.0 –0.5 −10 −50 −30 Max. 0.5 7.0 0.8 +10 +50 − 160 Unit V V V V µA µA mA Max. 10 12 12 Unit pF pF pF AC Test Loads and Waveforms 238Ω 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE (a) 170Ω 5V OUTPUT 238Ω 5 pF INCLUDING JIG AND SCOPE (b) Equivalent to: THÉVENIN EQUIVALENT OUTPUT 99Ω 2.08V 5 OR 35 pF 170Ω 5.0V GND <2 ns ALL INPUT PULSES 90% 10% 90% 10% <2 ns (c) Notes: 1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 3. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-02082 Rev. Page 5 of 8 5 Page

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