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P4C163L Schematic ( PDF Datasheet ) - Pyramid Semiconductor Corporation

Teilenummer P4C163L
Beschreibung ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS
Hersteller Pyramid Semiconductor Corporation
Logo Pyramid Semiconductor Corporation Logo 




Gesamt 12 Seiten
P4C163L Datasheet, Funktion
P4C163/P4C163L
ULTRA HIGH SPEED 8K x 9
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 25/35ns (Commercial)
– 25/35/45ns (Military)
Low Power Operation (Commercial/Military)
www.DataSheet4UO.coumtput Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C163L Military)
Common I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C163 and P4C163L are 73,728-bit ultra high-speed
static RAMs organized as 8K x 9. The CMOS memories re-
quire no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
With battery backup, data integrity is maintained for supply
voltages down to 2.0V. Current drain is 10 µA from a 2.0V
supply.
Access times as fast as 25 nanoseconds are available, per-
mitting greatly enhanced system operating speeds. CMOS
is used to reduce power consumption in both active and
standby modes.
The P4C163 and P4C163L are available in 28-pin 300 mil
DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin
CERPACK packages providing excellent board level densi-
ties.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5), SOJ (J5)
CERPACK (F4) SIMILAR
LCC (L5)
Document # SRAM120 REV C
Revised August 2006
1






P4C163L Datasheet, Funktion
P4C163/163L
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Symbol
Parameter
tWC Write Cycle Time
tCW Chip Enable
Time to End of Write
tAW Address Valid to
End of Write
tAS
tWP
tAH
www.DataSheett4DUW.com
Address Set-up Time
Write Pulse Width
Address Hold Time
Data Valid to End
of Write
tDH Data Hold Time
tWZ Write Enable to
Output in High Z
tOW Output Active
from End of Write
-25 -35 -45
Min Max Min Max Min Max
25 35 45
18 25 33
Unit
ns
ns
18 25 33 ns
0 0 0 ns
18 20 25 ns
0 0 0 ns
13 15 20 ns
0
10
0
14
0 ns
18 ns
3 5 5 ns
WRITE CYCLE NO. 1 (WE CONTROLLED)(11)
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE
HIGH, the output remains in a low impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM120 REV C
Page 6 of 12

6 Page









P4C163L pdf, datenblatt
P4C163/163L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
REV.
ISSUE
DATE
OR 1997
SRAM120
P4C164 / P4C163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
DAB
New Data Sheet
A Oct-05
JDB Change logo to Pyramid
B
www.DataSheet4U.com
C
Jul-06
Aug-06
JDB Added Lead-Free Designation
JDB Updated SOJ package information
Document # SRAM120 REV C
Page 12 of 12

12 Page





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