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PDF AD1933 Data sheet ( Hoja de datos )
| Número de pieza | AD1933 | |
| Descripción | 8 DAC | |
| Fabricantes | Analog Devices | |
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FEATURES
PLL generated or direct master clock
Low EMI design
DAC with 110 dB dynamic range and SNR
−96 dB THD + N
3.3 V single supply
Tolerance for 5 V logic inputs
www.DataSheeSt4uUp.pcoomrts 24 bits and 8 kHz to 192 kHz sample rates
Differential DAC output
Log volume control with autoramp function
SPI® controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes up to 16-channel input/output
64-lead LQFP
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
8 DAC with PLL,
192 kHz, 24-Bit Codec
AD1933
GENERAL DESCRIPTION
The AD1933 is a high performance, single chip that provides
eight digital-to-analog converters (DACs) with differential
output using the Analog Devices, Inc. patented multibit sigma-
delta (Σ-Δ) architecture. An SPI port is included, allowing a
microcontroller to adjust volume and many other parameters.
The AD1933 operates from 3.3 V digital and analog supplies.
The AD1933 is available in a 64-lead (differential output) LQFP.
Other members of this family include a single-ended DAC
output and I2C® control port version.
The AD1933 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR clock or from an external crystal, the AD1933 eliminates the
need for a separate high frequency master clock and can also be
used with a suppressed bit clock. The DACs are designed using
the latest Analog Devices continuous time architectures to
further minimize EMI. By using 3.3 V supplies, power
consumption is minimized, further reducing emissions.
DIGITAL AUDIO
INPUT/OUTPUT
AD1933
FUNCTIONAL BLOCK DIAGRAM
SERIAL
DATA
PORT
CLOCKS
SDATAIN
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PULL)
DIGITAL
FILTER
AND
VOLUME
CONTROL
PRECISION
VOLTAGE
REFERENCE
CONTROL PORT
I2C/SPI
CONTROL DATA
INPUT/OUTPUT
Figure 1.
6.144MHz
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
ANALOG
AUDIO
OUTPUTS
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
www.DataSheet4U.cPoomwer-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
AD1933
Conditions/Comments
DVDD
AVDD
VSUPPLY
Master clock = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
Min
3.0
3.0
4.5
Master clock = 256 fS, 48 kHz
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
Typ Max Unit
3.3 3.6
3.3 3.6
5.0 5.5
V
V
V
56 mA
65 mA
95 mA
2.0 mA
74 mA
23 mA
429 mW
185 mW
244 mW
83 mW
50 dB
50 dB
DIGITAL FILTERS
Table 6.
Parameter
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Mode
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
Factor
0.4535 fS
0.3646 fS
0.3646 fS
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
25/fS
11/fS
8/fS
Min Typ Max
22
35
70
±0.01
±0.05
±0.1
24
48
96
26
61
122
70
70
70
521
115
42
Unit
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
Rev. 0 | Page 5 of 28
5 Page 
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS (DACs)
The AD1933 DAC channels are arranged as differential,
four stereo pairs giving eight analog outputs for minimum
external components. The DACs include on-board digital
reconstruction filters with 70 dB stop-band attenuation and
linear phase response, operating at an oversampling ratio of
4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each
channel has its own independently programmable attenuator,
adjustable in 255 steps in increments of 0.375 dB. Digital inputs
are supplied through four serial data input pins (one for each
www.DataSheestt4eUre.coopmair) and a common frame clock (DLRCLK) and bit clock
(DBCLK). Alternatively, one of the TDM modes can be used to
access up to 16 channels on a single TDM data line.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A third-
order, external, low-pass filter is recommended to remove high
frequency noise present on the output pins. The use of op amps
with low slew rates or low bandwidths can cause high frequency
noise and tones to fold down into the audio band; therefore,
exercise care in selecting these components.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
The on-chip, phase-locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI/XI pin. The default at power-up
is 256 × fS from MCLKI/XI pin. In 96 kHz mode, the master
clock frequency stays at the same absolute frequency; therefore,
the actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if a
device in the AD1933 family is programmed in 256 × fS mode, the
frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.
If the AD1933 is then switched to 96 kHz operation (by writing
to the SPI or I2C port), the frequency of the master clock should
remain at 12.288 MHz, which becomes 128 × fS. In 192 kHz
mode, this becomes 64 × fS.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for DACs if selected in the PLL
and Clock Control 1 register.
AD1933
The PLL can be powered down in the PLL and Clock Control 0
register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and power it back up when the reference clock has
stabilized.
The internal master clock can be disabled in the PLL and Clock
Control 0 register to reduce power dissipation when the AD1933
is idle. The clock should be stable before it is enabled. Unless a
standalone mode is selected (see the Serial Control Port section),
the clock is disabled by reset and must be enabled by writing to
the SPI or I2C port for normal operation.
To maintain the highest performance possible, limit the clock
jitter of the internal master clock signal to less than a 300 ps rms
time interval error (TIE). Even at these levels, extra noise or
tones can appear in the DAC outputs if the jitter spectrum
contains large spectral peaks. If the internal PLL is not used, it
is highly recommended that an independent crystal oscillator
generate the master clock. In addition, it is especially important
that the clock signal not be passed through an FPGA, CPLD, or
other large digital chip (such as a DSP) before being applied to
the AD1933. In most cases, this induces clock jitter due to the
sharing of common power and ground connections with other
unrelated digital output signals. When the PLL is used, jitter in
the reference clock is attenuated above a certain frequency
depending on the loop filter.
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to their
default settings. To avoid pops, reset does not power down the
analog outputs. After RST is deasserted, and the PLL acquires
lock condition, an initialization routine runs inside the
AD1933. This initialization lasts for approximately 256 master
clock cycles.
The power-down bits in the PLL and Clock Control 0 and DAC
Control 1 registers power down the respective sections. All
other register settings are retained. To guarantee proper startup,
the RST pin should be pulled low by an external resistor.
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD1933.PDF ] | |
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