Datenblatt-pdf.com


ADUM5202 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADUM5202
Beschreibung (ADUM5200 - ADUM5202) Dual-Channel Isolators
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 23 Seiten
ADUM5202 Datasheet, Funktion
Preliminary Technical Data
Dual-Channel Isolators with
Integrated DC/DC Converter
ADuM5200/5201/5202
FEATURES
isoPower™ integrated isolated DC/DC converter
Regulated 3V or 5V output
500mW output power
Dual dc-to-25 Mbps (NRZ) signal isolation channels
Schmitt Trigger Inputs
www.DataSheeSt4OUIC.co1m6-lead package with > 8mm creepage
High temperature operation: 105°C
High common-mode transient immunity: > 25 kV/μs
Safety and regulatory approvals (pending)
UL recognition
2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
APPLICATIONS
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
Power Supply start up and Gate Drive
Isolated Sensor Interface
Industrial PLC
GENERAL DESCRIPTION
The ADuM520x1 are dual-channel digital isolators with
isoPower, an integrated, isolated DC/DC converter. Based on
Analog Devices’ iCoupler® technology, the DC/DC converter
provides up to 500 mW of regulated, isolated power at either
5.0V from a 5.0V input supply or 3.3V from a 3.3V or 5.0V
supply. This eliminates the need for a separate isolated DC/DC
converter in low-power isolated designs. Analog Devices’ chip-
scale transformer iCoupler technology is used both for the
isolation of the logic signals as well as for the DC/DC converter.
The result is a small form-factor total-isolation solution.
ADuM520x units may be used in combination with ADuM540x
and ADuM5000 with isoPower to achieve higher output power
levels and greater channel counts.
The ADuM520x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see Ordering Guide).
FUNCTIONAL BLOCK DIAGRAMS
Figure 1ADuM520x Functional Diagrams
1 Protected by U.S. Patents 5,952,849, 6,873,065. and 7075 329 B2, Other
patents pending.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.






ADUM5202 Datasheet, Funktion
ADuM5200/5201/5202
Parameter
Minimum Pulse Width13
Maximum Data Rate14
Propagation Delay15
Pulse-Width Distortion, |tPLH − tPHL|11
Change vs. Temperature
Propagation Delay Skew16
Channel-to-Channel Matching,
Codirectional Channels17
Channel-to-Channel Matching,
Opposing-Directional Channels17
Output Rise/Fall Time (10% to 90%)
www.DataCSohmeemt4oUn.c-Momode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
Refresh Rate
Symbol
PW
tPHL, tPLH
PWD
tPSK
tPSKCD
tPSKCD
tR/tF
|CMH|
|CML|
fr
Min
25
25
25
Preliminary Technical Data
Typ Max Unit Test Conditions
40 ns CL = 15 pF, CMOS signal levels
Mbps CL = 15 pF, CMOS signal levels
45 60
ns CL = 15 pF, CMOS signal levels
6
5
ns CL = 15 pF, CMOS signal levels
ps/°C CL = 15 pF, CMOS signal levels
45 ns CL = 15 pF, CMOS signal levels
6 ns CL = 15 pF, CMOS signal levels
15 ns CL = 15 pF, CMOS signal levels
2.5 ns CL = 15 pF, CMOS signal levels
35 kV/μs VIx = VDD or VISO, VCM = 1000 V,
transient magnitude = 800 V
35 kV/μs VIx = 0 V, V = 1000 V,
transient magnitude = 800 V
1.0 Mbps
1 All voltages are relative to their respective ground.
2 The contributions of supply current values for all four channels are combined at identical data rates.
3 VISO supply current available for external use when all data rates are below 2Mbps. At data rates above 2Mbps data I/O channels will draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget.
4 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of its internal power consumption.
5 IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2Mbps, requiring no
additional dynamic supply current. It reflects the minimum current operating condition.
6 IDD1(D) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum
dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load.
7 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at maximum data rate of 25Mbps with full capacitive load
representing the maximum dynamic load conditions. Refer to Power Consumption section for calculation of available current at less than maximum data rate.
8 IDD1(MAX) is the input current under full dynamic and VISO load conditions.
9 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
10 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
11 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
12 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
13 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
Rev. PrA| Page 6 of 23

6 Page









ADUM5202 pdf, datenblatt
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADuM5200/5201/5202
www.DataSheet4U.com
Figure 3. ADuM5200 Pin Configuration
Table 12. ADuM5200 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage 3.0V to 5.5 V.
2,8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3 VIA
Logic Input A.
4 VIB
Logic Input B.
5 RCIN Regulation Control Input, In slave power configuration (RCSEL=Low), this pin is connected to the RCOUT of a master
isoPower device, or tied low to disable the converter. In Master/Stand alone mode(RCSEL=High) this pin has no
function. This pin is weakly pulled to low. In Noisy environments it should be tied to low or to a PWM control source.
Warning -This pin must not be tied high if RCSEL is low, this combination will cause excessive volatge on the
secondary, damaging the ADuM5000 and possibly devices that it powers.
6
RCSEL
Control input, Determines self regulation (CTL High) mode or Slave mode(CTL Low)allowing external regulation. This
pin is weakly pulled to high. In noisy environments it should be tied either high or low.
7 NC
No Internal Connection
9,15 GNDISO Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10 VE2
Data Enable Input, When High or NC the Secondary outputs are active, when Low the outputs are in a high Z state..
11 VSEL
Output Voltage Selection: When VSEL = VISO then the Viso set point is 5.0V, When VSEL = GNDISO Then the VISO setpoint
is 3.3V. In Slave regulation mode, this pin has no function.
12 NC
No Internal Connection.
13 VOB
Logic Output B.
14 VOA
Logic Output A.
16 VISO
Secondary Supply Voltage Output for Secondary Isolaton electronics and External Loads, 3.3V (VSEL Low) or 5.0V (VSEL
High), 5.0V output Functioanlity not guaranteed for a 3.3V primary supply input.
Rev. PrA | Page 12 of 23

12 Page





SeitenGesamt 23 Seiten
PDF Download[ ADUM5202 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADUM5200(ADUM5200 - ADUM5202) Dual-Channel IsolatorsAnalog Devices
Analog Devices
ADUM5201(ADUM5200 - ADUM5202) Dual-Channel IsolatorsAnalog Devices
Analog Devices
ADUM5202(ADUM5200 - ADUM5202) Dual-Channel IsolatorsAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche