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A82DL1642T Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A82DL1642T
Beschreibung (A82DL16x2T) Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 30 Seiten
A82DL1642T Datasheet, Funktion
A82DL16x2T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,
A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only,
Simultaneous Operation Flash Memory and 2M (128Kx16 Bit) Static RAM
Preliminary
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Document Title
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit
(2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 2M
(128Kx16 Bit) Static RAM
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Update Figure 23
Issue Date
March 25, 2005
May 17, 2005
Remark
Preliminary
PRELIMINARY (May, 2005, Version 0.1)
AMIC Technology, Corp.






A82DL1642T Datasheet, Funktion
Flash Block Diagram
VCC_F
VSS
A82DL16x2T(U) Series
OE BYTE_F
A0-A19
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Upper Bank Address
RY/BY
Upper Bank
A0-A19
RESET
WE
CE_F
BYTE_F
WP/ACC
I/O0-I/O15
STATE
CONTROL
&
COMMAND
REGISTER
X-Decoder
Status
Control
X-Decoder
A0-A19
Lower Bank Address
Upper Bank
OE BYTE_F
I/O0-I/O15
PRELIMINARY (May, 2005, Version 0.1)
5
AMIC Technology, Corp.

6 Page









A82DL1642T pdf, datenblatt
A82DL16x2T(U) Series
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
sleep mode is independent of the CE_F , WE and OE
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the
system. ICC4_F in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET : Hardware Reset Pin
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The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws
CMOS standby current (ICC4_F ). If RESET is held at VIL but
not within VSS ± 0.3V, the standby current will be greater.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/ BY pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
RY/ BY to determine whether the reset operation is
complete. If RESET is asserted when a program or erase
operation is not executing (RY/ BY pin is “1”), the reset
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
Device
Part Number
A82DL1622
A82DL1632
A82DL1642
Table 2. A82DL16x2T(U) Device Bank Divisions
Megabits
2 Mbit
4 Mbit
8 Mbit
Bank 1
Sector Sizes
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Megabits
14 Mbit
12 Mbit
8 Mbit
Bank 2
Sector Sizes
Twenty-eight
64 Kbyte/32 Kword
Twenty-four
64 Kbyte/32 Kword
Sixteen
64 Kbyte/32 Kword
PRELIMINARY (May, 2005, Version 0.1)
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AMIC Technology, Corp.

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