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DS32EV400 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DS32EV400
Beschreibung Programmable Single Equalizer
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
DS32EV400 Datasheet, Funktion
October 2007
DS32EV400
Programmable Quad Equalizer
General Description
The DS32EV400 programmable quad equalizer provides
compensation for transmission medium losses and reduces
the medium-induced deterministic jitter for four NRZ data
channels. The DS32EV400 is optimized for operation up to
3.2 Gbps for both cables and FR4 traces. Each equalizer
channel has eight levels of input equalization that can be pro-
grammed by three control pins, or individually through a Serial
www.DataSheeMt4aUn.caogmement Bus (SMBus) interface.
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and bal-
anced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs, and is available
in a 7 mm x 7 mm 48-pin leadless LLP package. Power is
supplied from either a 2.5V or 3.3V supply.
Features
Equalizes up to 14 dB loss at 3.2 Gbps
8 levels of programmable equalization
Settable through control pins or SMBus interface
Operates up to 3.2 Gbps with 40” FR4 traces
0.12 UI residual deterministic jitter at 3.2 Gbps with 40”
FR4 traces
Single 2.5V or 3.3V power supply
Signal Detect for individual channels
Standby mode for individual channels
Supports AC or DC-Coupling with wide input common-
mode
Low power consumption: 375 mW Typ at 2.5V
Small 7 mm x 7 mm 48-pin LLP package
9 kV HBM ESD
-40 to 85°C operating temperature range
Simplified Application Diagram
© 2007 National Semiconductor Corporation 300319
30031924
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DS32EV400 Datasheet, Funktion
Symbol
Parameter
Conditions
Min Typ Max Units
SIGNAL DETECT and ENABLE TIMING
tZISD
tIZSD
TRI-STATE to Input SD Delay
Input to TRI-STATE SD Delay
Propagation delay measurement
at VIN to SD output, VIN = 800
mVP-P, 100 Mbps, 40” of 6 mil
microstrip FR4
(Figure 1, 4)
(Note 7)
35
400
ns
ns
tOZOED
tZOED
EN TRI-STATE to Output Delay
EN output to TRI-STATE Delay
Propagation delay measurement
at EN input to VO, VIN = 800 mVP-
P, 100 Mbps, 40” of 6 mil microstrip
FR4
(Figure 1, 4)
(Note 7)
150
5
ns
ns
www.DataSheet4U.cNoomte 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. Absolute Maximum Numbers are guaranteed for a junction temperature range of –40°C to +125°C. Models
are validated to Maximum Operating Voltages only.
Note 2: Typical values represent most likely parametric norms at VDD = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Allowed supply noise (mVP-P sine wave) under typical conditions.
Note 5: Specification is guaranteed by characterization and is not tested in production.
Note 6: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).
Random jitter is removed through the use of averaging or similar means.
Note 7: Measured with clock like {11111 00000} pattern.
Note 8: Random jitter contributed by the equalizer is defined as sqrt (JOUT2 − JIN2). JOUT is the random jitter at the equalizer outputs in ps-rms, see point C of
Figure 1; JIN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.
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DS32EV400 pdf, datenblatt
DEVICE STATE AND ENABLE CONTROL
The DS32EV400 has an Enable feature on each data channel
which provides the ability to control device power consump-
tion. This feature can be controlled either via each Enable Pin
(ENn Pin) or via the Enable Control Bit which is accessed
through the SMBus port (see Table 1 and Table 3). If the En-
able is activated, the corresponding data channel is placed in
the ACTIVE state and all device blocks function as described.
The DS32EV400 can also be placed in STANDBY mode to
save power. In this mode only the control interface including
the SMBus port, as well as the signal detection circuit remain
active.
TABLE 3. Controlling Device State
Register 07[0]
(SMBus)
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EN Pin
(CMOS)
Channel 0:
Register 03[3]
Channel 1:
Register 03[7]
Channel 2:
Register 04[3]
Channel 3:
Register 04[7]
(EN Control)
(SMBus)
Device State
0 : Disable
1
X ACTIVE
0 : Disable
0
X STANDBY
1 : Enable
X
0 ACTIVE
1 : Enable
X
1 STANDBY
SIGNAL DETECT
The DS32EV400 features a signal detect circuit on each data
channel. The status of the signal of each channel can be de-
termined by either reading the Signal Detect bit (SDn) in the
SMBus registers (see Table 1) or by the state of each SDn
pin. A logic High indicates the presence of a signal that has
exceeded a specified maximum threshold value (called
SD_ON). A logic Low means that the input signal has fallen
below a minimum threshold value (called SD_OFF). These
values are programmed via the SMBus (Table 1). If not pro-
grammed via the SMBus, the minimum and maximum thresh-
olds take on the default values for the minimum and maximum
values as indicated in Table 4. The Signal Detect threshold
values can be changed through the SMBus. All threshold val-
ues specified are DC peak-to-peak differential signals (posi-
tive signal minus negative signal) at the input of the device.
TABLE 4. Signal Detect Threshold Values
Channel 0:
Bit 1
Channel 1:
Bit 3
Channel2:
Bit 5
Channel 3:
Bit 7
Channel 0:
Bit 0
Channel 1:
Bit 2
Channel2:
Bit 4
Channel 3:
Bit 6
Minimum
Threshold
Register 06
(mV)
Maximum
Threshold
Register 05
(mV)
0 0 40 (Default) 70 (Default)
0 1 30 55
1 0 55 90
1 1 45 75
OUTPUT LEVEL CONTROL
The output amplitude of the CML drivers for each channel can
be controlled via the SMBus (see Table 1). The default output
level is 650 mVp-p. The following Table presents the output
level values supported:
TABLE 5. Output Level Control Settings
All Channels: Bit 3 All Channels: Bit 2
00
Output Level
Register 08
(mVP-P)
400
0 1 540
1 0 620 (Default)
1 1 760
AUTOMATIC ENABLE FEATURE
It may be desirable to place unused channels in power-saving
Standby mode. This can be accomplished by connecting the
Signal detect (SDn) pin to the Enable (ENn) pin for each
channel (See Figure 7). In order for this option to function
properly, the FEB pin must be either tied High or not connect-
ed (the FEB pin is internally pulled High by default). If an input
signal swing applied to a data channel is above the maximum
level specified in the threshold register via the SMBus, then
the SDn pin is asserted High. If the SDn pin is connected to
the ENn pin, this will enable the equalizer, limiting amplifier,
and output buffer on the data channels (provided that the FEB
pin is High); thus the DS32EV400 will automatically enter the
ACTIVE state. If the input signal swing falls below the mini-
mum level specified in the threshold register, then the SDn
pin will be asserted Low, causing the aforementioned blocks
to be placed in the STANDBY state.
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