Datenblatt-pdf.com


P4C1024L Schematic ( PDF Datasheet ) - Pyramid Semiconductor

Teilenummer P4C1024L
Beschreibung LOW POWER 128K x 8 CMOS STATIC RAM
Hersteller Pyramid Semiconductor
Logo Pyramid Semiconductor Logo 




Gesamt 11 Seiten
P4C1024L Datasheet, Funktion
P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
www.DataSheet4UE.caomsy Memory Expansion Using CE1, CE2 and OE
Inputs
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
FUNCTIONAL BLOCK DIAGRAM
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE1 or OE is HIGH or WE or CE2 is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, and a 600 mil PDIP.
PIN CONFIGURATION
DIP (P600, C10), SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document # SRAM125 REV C
Revised September 2006
1






P4C1024L Datasheet, Funktion
P4C1024L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
www.DataSheet4U.com
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Fig. 1 and 2
TRUTH TABLE
Mode
Standby
Standby
CE1 CE2 OE WE
H XXX
X LXX
DOUT Disabled L H H H
Read
LHLH
Write
L HX L
I/O
High Z
High Z
High Z
DOUT
DIN
Power
Standby
Standby
Active
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the high speed of the P4C1024L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC
and ground planes directly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required between VCC and ground.
Figure 2. Thevenin Equivalent
To avoid signal reflections, proper termination must be used; for
example, a 50test environment should be terminated into a 50
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589resistor must be used in series with DOUT to match 639
(Thevenin Resistance).
Document # SRAM125 REV C
Page 6 of 10

6 Page







SeitenGesamt 11 Seiten
PDF Download[ P4C1024L Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
P4C1024HIGH SPEED 128K X 8 CMOS STATIC RAMETC
ETC
P4C1024-15J3CHIGH SPEED 128K X 8 CMOS STATIC RAMETC
ETC
P4C1024-15J3IHIGH SPEED 128K X 8 CMOS STATIC RAMETC
ETC
P4C1024-15J4CHIGH SPEED 128K X 8 CMOS STATIC RAMETC
ETC
P4C1024-15J4IHIGH SPEED 128K X 8 CMOS STATIC RAMETC
ETC

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche