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PDF DS1992 Data sheet ( Hoja de datos )
| Número de pieza | DS1992 | |
| Descripción | (DS1992 / DS1993) 1kbit/4kbit Memory iButtonTM DS1994 4-kbit Plus Time Memory iButtonTM | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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www.iButton.com
SPECIAL FEATURES
§ 4096 bits of Read/Write Nonvolatile
Memory (DS1993)
§ 1024 bits of Read/Write Nonvolatile
Memory (DS1992)
§ 256-bit Scratchpad Ensures Integrity of Data
www.DataSheet4TUr.caonmsfer
§ Memory Partitioned into 256-bit Pages for
Packetizing Data
§ Data Integrity Assured with Strict
Read/Write Protocols
§ Operating Temperature Range from -40°C to
+70°C
§ Over 10 years of data retention
COMMON iButton FEATURES
§ Unique, Factory-Lasered and Tested 64-bit
Registration Number (8-bit Family Code +
48-bit Serial Number + 8-bit CRC Tester)
Assures Absolute Traceability Because No
Two Parts are Alike
§ Multidrop Controller for MicroLAN
§ Digital Identification and Information by
Momentary Contact
§ Chip-Based Data Carrier Compactly Stores
Information
§ Data Can be Accessed While Affixed to
Object
§ Economically Communicates to Bus Master
with a Single Digital Signal at 16.3kbps
§ Standard 16mm Diameter and 1-Wire®
Protocol Ensure Compatibility with iButton®
Family
§ Button Shape is Self-Aligning with Cup-
Shaped Probes
§ Durable Stainless Steel Case Engraved with
Registration Number Withstands Harsh
Environments
DS1992/DS1993
1kb/4kb Memory iButton
§ Easily Affixed with Self-Stick Adhesive
Backing, Latched by its Flange, or Locked
with a Ring Pressed onto its Rim
§ Presence Detector Acknowledges When
Reader First Applies Voltage
§ Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations
F5 MICROCAN
5.89
0.36 0.51
© 1993
YYWW REGISTERED RR
DD 06
000000FBD804
16.25
17.35
IO
GND
All dimensions shown in millimeters.
ORDERING INFORMATION
DS1992L-F5
F5 MicroCan
DS1993L-F5
F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P Self-Stick Adhesive Pad
DS9101 Multipurpose Clip
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
DS9092 iButton Probe
1-Wire and iButton are registered trademarks of Dallas Semiconductor.
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021604
1 page  
DS1992/DS1993
MEMORY
The memory map in Figure 4 shows a 32-Byte page called the scratchpad, and additional 32-Byte pages
called memory. The DS1992 contains pages 0 though 3 that make up the 1024-bit SRAM. The DS1993
contain pages 0 through 15 that make up the 4096-bit SRAM.
The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
transfers the data to memory. This process ensures data integrity when modifying the memory.
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the memory.
An example follows the flow chart. Three address registers are provided as shown in Figure 5. The first
two registers represent a 16-bit target address (TA1, TA2). The third register is the ending offset/data
www.DataShsetaett4uUs.cboymte (E/S).
The target address points to a unique Byte location in memory. The first 5 bits of the target address
(T4:T0) represent the Byte offset within a page. This Byte offset points to one of 32 possible Byte
locations within a given page. For instance, 00000b points to the first Byte of a page where as 11111b
would point to the last Byte of a page.
The third register (E/S) is a read only register. The first 5 bits (E4: E0) of this register are called the
ending offset. The ending offset is a Byte offset within a page (1 of 32 Bytes). Bit 5 (PF) is the partial
Byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag.
Figure 5. ADDRESS REGISTERS
TARGET ADDRESS (TA1)
76543210
T7 T6 T5 T4 T3 T2 T1 T0
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
T15 T14 T13 T12 T11 T10 T9
AA OF PF E4 E3 E2 E1
T8
E0
Write Scratchpad Command [0Fh]
After issuing the write scratchpad command, the user must first provide the 2-Byte target address,
followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the
byte offset (T4:T0). The ending offset (E4:E0) is the Byte offset at which the host stops writing data. The
maximum ending offset is 11111b (31d). If the host attempts to write data past this maximum offset, the
overflow flag (OF) is set and the remaining data is ignored. If the user writes an incomplete Byte and an
overflow has not occurred, the partial Byte flag (PF) is set.
Read Scratchpad Command [AAh]
This command can be used to verify scratchpad data and target address. After issuing the read scratchpad
command, the user can begin reading. The first two Bytes are the target address. The next Byte is the
ending offset/data status Byte (E/S) followed by the scratchpad data beginning at the Byte offset (T4: T0).
The user can read data until the end of the scratchpad, after which the data read is all logic 1’s.
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5 Page 
DS1992/DS1993
slave(s). The presence pulse lets the bus master know that the DS199_ is on the bus and is ready to
operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All
ROM function commands are 8 bits long. A list of these commands follows (see the flow chart in Figure
9).
Read ROM [33h]
This command allows the bus master to read the DS199_’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command should only be used if there is a single DS199_ on the bus. If
more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the
www.DataShseaemt4eU.tciomme (open drain produces a wired-AND result). The resultant family code and 48-bit serial number
usually result in a mismatch of the CRC.
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS199_ on a multidrop bus. Only the DS199_ that exactly matches the 64-bit ROM sequence
will respond to the following memory function command. All slaves that do not match the 64-bit ROM
sequence wait for a reset pulse. This command can be used with single or multiple devices on the bus.
Skip ROM [CCh]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and, for example, a read command is issued following the Skip ROM command, data collision will occur
on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND
result).
Search ROM [F0h]
When a system is initially brought up, the bus master may not know the number of devices on the 1-Wire
bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of
elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is
the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one
complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify
the ROM codes of the remaining devices. See Chapter 5 of the Book of DS19xx iButton Standards for a
comprehensive discussion of a search ROM, including an actual example.
1-WIRE SIGNALING
The DS199_ require strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data.
The bus master initiates all these signals except presence pulse. The initialization sequence required to
begin any communication with the DS199_ is shown in Figure 10. A reset pulse followed by a presence
pulse indicates the DS199_ is ready to send or receive data given the correct ROM command and
memory function command. The bus master transmits (Tx) a reset pulse (tRSTL, minimum 480ms). The bus
master then releases the line and goes into receive mode (Rx). The 1-Wire bus is pulled to a high state
through the pullup resistor. After detecting the rising edge on the data line, the DS199_ waits (tPDH, 15ms
to 60ms) and then transmits the presence pulse (tPDL, 60ms to 240ms).
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11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet DS1992.PDF ] | |
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