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PDF PM6670 Data sheet ( Hoja de datos )

Número de pieza PM6670
Descripción Complete DDR2/3 memory power supply controller
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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PM6670
Complete DDR2/3 memory power supply controller
Preliminary Data
Features switching
Switching section (VDDQ)
www.DataSheet4U.com– 4.5V to 28V input voltage range
– 0.9V, ±1% voltage reference
– 1.8V (DDR2) or 1.5V (DDR3) fixed output
voltages
– 0.9V to 2.6V adjustable output voltage
– 1.237V ±1% reference voltage available
– Very fast load transient response using
constant on-time control loop
– No RSENSE current sensing using low side
MOSFET’s RDS(ON)
– Negative current limit
– Latched OVP and UVP
– Soft start internally fixed at 3ms
– Selectable pulse skipping at light load
– Selectable No-Audible (33KHz) pulse skip
mode
– Ceramic output capacitors supported
– Output voltage ripple compensation
VTT LDO and VTTREF
– 2Apk LDO with foldback for VTT
– Remote VTT sensing
– High-Z VTT output in S3
– Ceramic output capacitors supported
– ±15mA Low noise buffered reference
Applications
DDR2/3 memory supply
Notebook computers
Handheld and PDAs
CPU and chipset I/O supplies
SSTL18, SSTL15 and HSTL bus termination
VFQFPN-24 4x4
Description
The device PM6670 is a complete DDR2/3 power
supply regulator designed to meet JEDEC
specifications.
It integrates a Constant On-Time (C.O.T.) buck
controller, a 2Apk sink/source Low Drop Out
regulator and a 15mA low noise buffered
reference.
The C.O.T. architecture assures fast transient
response supporting both electrolytic and ceramic
output capacitors. An embedded integrator
control loop compensates the DC voltage error
due to the output ripple.
The 2Apk sink/source linear regulator provides
the memory termination voltage with fast load
transient response.
The device is fully compliant with system sleep
states S3 and S4/S5, providing LDO output high
impedance in Suspend-To-RAM and Tracking
Discharge of all outputs in Suspend-To-Disk.
Table 1. Device summary
Part number
PM6670
Package
VFQFPN-24 4x4 (Exposed Pad)
Packaging
Tube
March 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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www.st.com
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PM6670 pdf
PM6670
2 Pin settings
2.1 Connections
Figure 2. Pin connection (through top view)
Pin settings
www.DataSheet4U.com
24
1
VTTGND
VTTSNS
DDRSEL
VTTREF
SGND
AVCC
6
7
PM6670
19
18
VCC
LGATE
PGND
PG
S3
S5
13
12
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PM6670 arduino
PM6670
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Soft end section
www.DataSheet4U.com
VDDQ Discharge resistance
in non-tracking discharge
mode
VTT discharge resistance in
non-tracking discharge mode
VTTREF discharge
resistance in non-tracking
discharge mode
VDDQ Output threshold
synchronous for final tracking
to non-tracking discharge
transition
VTT LDO section
ILDOIN,ON
LDO input bias current in
full-on state
S3 = S5 = +5V, No Load on VTT
ILDOIN, LDO input bias current in
STR suspend-to-RAM state
ILDOIN, LDO input bias current in
STD suspend-to-disk state
IVTTSNS, VTTSNS bias current
BIAS
S3 = 0V, S5 = +5V,
No Load on VTT
S3 = S5 = 0V, No Load on VTT
S3 = +5V, S5 = +5V,
VVTTSNS = VVSNS /2
IVTTSNS, VTTSNS leakage current
LEAK
S3 = 0V, S5 = +5V,
VVTTSNS = VVSNS /2
IVTT,LEAK VTT leakage current
S3 = 0V, S5 = +5V,
VVTT = VVSNS /2
LDO linear regulator output S3 = S5= +5V, IVTT = 0A,
voltage (DDR2)
MODE = DDRSEL = +5V
LDO linear regulator output S3 = S5= +5V, IVTT = 0A,
voltage (DDR3)
MODE = +5V, DDRSEL = 0V
VVTT
S3 = S5 = MODE = + 5V,
-1mA < IVTT < 1mA
LDO output accuracy respect S3 = S5 = MODE = +5V,
to VTTREF
-1A < IVTT < 1A
S3 = S5 = MODE = +5V,
-2A < IVTT < 2A
LDO source current limit
IVTT,CL
LDO sink current limit
VVTT < 1.10*( VVSNS /2)
VVTT > 1.10*( VVSNS /2)
VVTT > 0.90*( VVSNS /2)
VVTT < 0.90*( VVSNS /2)
Electrical characteristics
Values
Min Typ Max
Unit
15 25 35
15 25 35
1 1.5 2 k
0.2 0.4 0.6
V
1 10
10
1
µA
1
1
-10 10
0.9
V
0.75
-20 20
-25 25 mV
-35
2 2.3
1 1.15
-2.8 -2.3
-1.4 -1.15
35
2.8
1.4
-2
-1
A
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