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89LP4052 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer 89LP4052
Beschreibung AT89LP4052
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 30 Seiten
89LP4052 Datasheet, Funktion
Features
Compatible with MCS®51 Products
20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85°C Operating Conditions
Single Clock Cycle per Byte Fetch
2/4K Bytes of In-System Programmable (ISP) Flash Memory
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 32-byte User Signature Array
2.4V to 5.5V VCC Operating Range
Fully Static Operation: 0 Hz to 20 MHz
2-level Program Memory Lock
256 x 8 Internal RAM
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15 Programmable I/O Lines
Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
Enhanced UART with Automatic Address Recognition and Framing Error Detection
Enhanced SPI with Double-buffered Send/Receive
Programmable Watchdog Timer with Software Reset
4-level Interrupt Priority
Analog Comparator with Selectable Interrupt and Debouncing
Two 16-bit Enhanced Timer/Counters with 8-bit PWM
Brown-out Detector and Power-off Flag
Internal Power-on Reset
Low Power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
8-bit
Microcontroller
with 2/4-Kbyte
Flash
AT89LP2052
AT89LP4052
1. Description
The AT89LP2052/LP4052 is a low-power, high-performance CMOS 8-bit microcon-
troller with 2/4K bytes of In-System Programmable Flash memory. The device is
manufactured using Atmel's high-density nonvolatile memory technology and is com-
patible with the industry-standard MCS-51 instruction set. The AT89LP2052/LP4052
is built around an enhanced CPU core that can fetch a single byte from memory every
clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forc-
ing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP2052/LP4052
CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more through-
put than the standard 8051. Seventy percent of instructions need only as many clock
cycles as they have bytes to execute, and most of the remaining instructions require
only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput
whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consump-
tion. Conversely, at the same throughput as the classic 8051, the new CPU core runs
at a much lower speed and thereby greatly reduces power consumption.
3547F–MICRO–6/06






89LP4052 Datasheet, Funktion
6. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table 6-1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect. User software should not write to these unlisted
locations, since they may be used in future products to invoke new features.
Table 6-1.
0F8H
AT89LP2052/LP4052 SFR Map and Reset Values
0FFH
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0000 0000
0E8H
0F7H
0EFH
0E0H
0D8H
ACC*
0000 0000
0E7H
0DFH
0D0H
0C8H
PSW*
0000 0000
SPCR
0000 0000
0D7H
0CFH
0C0H
0B8H
0B0H
0A8H
0A0H
IP*
x0x0 0000
P3*
1111 1111
IE*
00x0 0000
98H SCON*
0000 0000
90H P1*
1111 1111
88H TCON*
0000 0000
80H
SADEN
0000 0000
SADDR
0000 0000
SBUF
xxxx xxxx
TCONB
0010 0100
TMOD
0000 0000
SP
0000 0111
P1M0
1111 1111
SPSR
000x xx00
RL0
0000 0000
TL0
0000 0000
DPL
0000 0000
P1M1
0000 0000
RL1
0000 0000
TL1
0000 0000
DPH
0000 0000
RH0
0000 0000
TH0
0000 0000
P3M0
1111 1111
WDTRST
(write-only)
RH1
0000 0000
TH1
0000 0000
SPDR
xxxx xxxx
P3M1
0000 0000
0C7H
0BFH
IPH
x0x0 0000
0B7H
0AFH
WDTCON
0000 x000
0A7H
9FH
ACSR
xx00 0000
97H
8FH
PCON 87H
000x 0000
Note: *These SFRs are bit-addressable.
6 AT89LP2052/LP4052
3547F–MICRO–6/06

6 Page









89LP4052 pdf, datenblatt
12.1 Idle Mode
Setting the IDL bit in PCON enters Idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. The Timer, UART and SPI blocks continue to function dur-
ing Idle. The comparator and watchdog may be selectively enabled or disabled during Idle. Any
enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an inter-
rupt, the interrupt will immediately be serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put the device into Idle.
12.2 Power-down Mode
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Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator and powers down the Flash memory in order to minimize power consumption. Only
the power-on circuitry will continue to draw power during Power-down. During Power-down, the
power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be
retained, but the SFR contents are not guaranteed once VCC has been reduced. Power-down
may be exited by external reset, power-on reset, or certain interrupts.
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 µs
until after one of the following conditions has occurred: Start of code execution (after any type of
reset), or Exit from power-down mode.
12.2.1
Interrupt Recovery from Power-down
Two external interrupts may be configured to terminate Power-down mode. Pins P3.2 and P3.3
may be used to exit Power-down through external interrupts INT0 and INT1. To wake up by
external interrupts INT0 or INT1, that interrupt must be enabled and configured for level-sensi-
tive operation. If configured as inputs, INT0 and INT1 should not be left floating during Power-
down even if interrupt recovery is not used.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed. At the falling edge on the
interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins count-
ing. The internal clock will not be allowed to propagate to the CPU until after the timer has
counted for nominally 2 ms. After the time-out period the interrupt service routine will begin. The
interrupt pin may be held low until the device has timed out and begun executing, or it may
return high before the end of the time-out period. If the pin remains low, the service routine
should disable the interrupt before returning to avoid re-triggering the interrupt.
When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, Power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin. The interrupt should
be held low long enough for the selected clock source to stabilize.
12.2.2
Reset Exit from Power-down
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has counted for nominally 2 ms. The RST pin must be held high for longer
than the time-out period to ensure that the device is reset properly. The device will begin execut-
ing once RST is brought back low.
12 AT89LP2052/LP4052
3547F–MICRO–6/06

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