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PDF DMI3110A Data sheet ( Hoja de datos )
| Número de pieza | DMI3110A | |
| Descripción | Digital MAC Interface | |
| Fabricantes | Micronas | |
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MICRONAS
INTERMETALL
DMI 3110 A
Digital MAC Interface
Edition Nov. 8, 1996
6251-381-2DS
MICRONAS
1 page  
DMI 3110 A
2.2. Automatic Gain Control
The AGC circuit controls the gain for the analog input
signal and feeds the controlled signal to the following
A/D converter. The input voltage can vary in the range
from 0.5 Vpp to 2 Vpp (1 Vpp$6 dB). The amplitude of the
A/D converter output signal will be measured in the
D2MAC decoder circuit and read from a central control
unit (CCU) over the I2C-bus to calculate the gain control
signal. The measurement will be done in line 624, there-
fore the digital baseband input signal for the D2MAC de-
coder should not be influenced by other circuits during
www.DataSheett4hUis.colimne.
The gain control itself is done by a digital gain controlled
amplifier in front of the A/D converter. The gain range
of$6 dB is logarithmically scaled in 64 steps with a step
size of 0.19 dB. As the control algorithm is done by soft-
ware in the CCU, features of the AGC, such as histories
and backlash functions can also be provided easily.
2.3. Clamping
The clamping circuit clamps the analog input signal to a
fixed level. The offset value of the digital MAC signal is
measured in the D2MAC decoder and the clamping sig-
nal is fed to the DMI circuit as 4-bit PDM (Pulse Density
Modulated) signal. In the DMI a clamping current is gen-
erated for the coupling capacitors at the MAC inputs. For
proper functioning of the clamping it is required to con-
nect no circuit with an extra clamping function between
the digital MAC output of the DMI and the input of the
D2MAC decoder.
2.4. A/D Converter
The A/D converter is an 8-bit two-step flash converter
which runs at 20.25 MHz. The output signal is purely
binary-coded and is fed to the D2MAC decoder. Option-
ally, the signal can be selected to become Gray code for-
mat. The reference voltage is internally generated and
is connected to one pin for a decoupling capacitor. The
A/D converter (and the D/A converters) are connected
to extra 5V and ground pins for a supply with a separate
low-noise supply voltage. The analog MAC input signal
must be AC-coupled over a coupling capacitor.
2.5. PAL Encoder
The PAL encoder receives the digital 4:2:2 component
signal (YUV) from the D2MAC decoder. The encoder is
also connected to the on-screen display (OSD) format-
ter and to the Teletext transcoder. These signals will be
coded into a composite video signal in the PAL standard.
Three D/A converters produce the composite video sig-
nal, the chrominance signal and the luminance signal.
2.6. Teletext Transcoder
The DMI can handle D2MAC Teletext signals trans-
mitted in the vertical blanking interval (VBI). In the trans-
coder, the Teletext signal is extracted from the D2MAC
data signal. The data rate and signal timing are con-
verted according to the WST Teletext standard. Teletext
transcoding is active in TV lines 6 to 22 and 319 to 335
of the PAL signal. Thus not all lines that can carry Tele-
text in the D2MAC standard (2 to 22 and 314 to 334) are
transcoded.
A generator in the transcoder generates the correct
Teletext bit frequency. A programmable window for en-
abling the Teletext transcoding will be available. The
start and stop times of this window can be programmed
between lines 6 and 22 (319 and 335) to span all Teletext
lines in the PAL standard. For proper synchronization
the MAC Sync signal from the D2MAC decoder will be
used.
2.7. OSD Formatter and Insertion
An external on-screen signal (e.g. from the TPU 2735)
can be fed into the DMI. The signal is 3 1 bit RGB and
Fast Blanking. These input signals are sampled with the
double clock frequency and processed with a downsam-
pling filter to the single clock frequency. In the OSD for-
matter the 3-bit RGB signals are converted to YUV com-
ponent signals, 6 bit for Y, 5 bit for U and 5 bit for V. This
is done in a user-programmable RAM with a size of
8 16 bit. Contrast, brightness and saturation of the
OSD can be programmed in this way. The output signal
of the OSD formatter is fed into the PAL encoder and into
the RGB/YUV outputs. The OSD can be switched off
separately for PAL and RGB/YUV.
2.8. Luminance Offset Subtracter
The digital luminance signal coming from the D2MAC
decoder has an offset of)16. This means that the black
level is shifted to this value. At the luminance input of the
DMI 3110 A a value of 16 can be subtracted from the lu-
minance signal. Therefore, the range of the luminance
signal is from 0 to 238. The D/A output range is set to
0.75 V for full-scale (255) input, hence the amplitude of
238 gives 0.7 V at the output.
2.9. Equalization Delay
The PAL encoder has a processing delay of some micro-
seconds. For a time matching between the analog RGB
signals and the Y, C and CVBS signals an equalization
delay exists. This delay is adjustable because the en-
coder delay depends on the filter settings.
MICRONAS INTERMETALL
5
5 Page 
DMI 3110 A
3.3. Pin Descriptions
Pin 1 to 3 and 64 to 68 – Digital Baseband Outputs
(Interface to DMA, see Fig. 3-9):
Via these pins the DMA circuits will be supplied with the
digitized MAC baseband signal. The code of the signal
is 8-bit pure binary.
Pin 4 – Digital Supply Voltage:
This pin supplies all digital stages and has to be con-
nected with the positive supply voltage.
www.DataSheetP4Uin.c5om– Digital Ground:
This is the common ground connection of all digital
stages and has to be connected with the ground of the
power supply.
Pin 6 – Clamping Input (Interface to DMA, Fig. 3–3):
To this pin the DMA supplies a PDM (Pulse Density Mod-
ulated) signal for clamping the analog MAC baseband
signal at the input of the AGC amplifier. This pin has to
be connected to pin 48 of the DMA circuit.
Pin 7 – Main Clock Output (Supply of DMA and others,
Fig. 3–10):
This pin is the output of the main clock generator. The
clock generator drives all circuits with the synchronized
clock signal. The clock frequency is 20.25 MHz.
Pin 8 to 15 – Digital Luma Inputs (Interface to DMA, Fig.
3–2):
Via these pins the DMI gets the digital luminance signal
in 8-bit pure binary code from the DMA circuit. All bits
equal to zero means black, all bits equal to one means
white.
Pins 16 to 19 and 22 to 25 – Digital Chroma Inputs (Inter-
face to DMA, Fig. 3–2):
Via these pins the DMI gets the digital chrominance sig-
nal from the DMA circuit. The code is 8-bit two’s comple-
ment. The components U and V are multiplexed, which
means that the data rate of each component signal is
10.125 MHz.
Pin 20 – PLL Tuning Clock Input
(Interface to DMA, see Fig. 3–3):
This pin gets the clock for the PLL tuning data signal
from the DMA. This pin has to be connected with the pin
26 of the DMA circuit.
Pin 21 – PLL Tuning Data Input (Interface to DMA, Fig.
3–3):
This pin gets the data signal for the clock generation PLL
from the DMA. The signal is a 12-bit serial data word
which will be loaded into a shift register. The data con-
tains the information for the frequency adjustment of the
clock generator. The data format is compatible with the
MCU 2600 clock generator. The clock phase will be
compared with the phase of the MAC signal clock in the
DMA circuit. This pin has to be connected with pin 25 of
the DMA circuit.
MICRONAS INTERMETALL
Pin 26 – Reset Input (Fig. 3–4):
A low signal at this pin generates a reset. The low-high
transition of this signal should come when the supply
voltage is stable (power-on reset). The input has Schmitt
trigger characteristics.
Pin 27 and 28 – XTAL 1/2 (Fig. 3–8):
The 20.25 MHz crystal is connected with these two pins.
Pin 27 is the input and pin 28 is the output of the oscillator
circuit. Both pins need an external capacitor to ground.
Pin 29 – Composite Sync Input (Interface to DMA, Fig.
3–2):
This pin gets the composite sync signal from the DMA.
This signal is used as synchronization signal in the PAL
coder of the DMI and has to be connected to pin 53 of
the DMA circuit.
Pins 30 and 31 – MAC Data and Sync Input (Interface to
DMA, Fig. 3–3):
Via this pin the VBI Teletext signal will be supplied from
the DMA. The burst data signal contains the binary tele-
text data in lines 2 to 22 and lines 314 to 334 of the
D2MAC signal. The burst sync signal synchronizes the
teletext data. Pin 30 has to be connected to pin 59 and
pin 31 has to be connected to pin 58 of the DMA circuit.
Pins 32, 33, 38 to 41 – Test Pins:
These pins are for test purposes only. In normal opera-
tion the pins 32, 33, 40, and 41 have to be connected to
ground.
Pins 34 to 37 – On-screen Display Inputs (Fig. 3–3):
Via these pins the DMI will be supplied with the on-
screen signals. Three inputs are for the one-bit RGB sig-
nals, the fourth input is for the fast blanking signal. A high
level at the fast blanking input enables the OSD signal.
This can be inserted (switchable) into all analog output
signals of the DMI. The input signals are sampled with
twice the clock frequency (40.5 MHz).
Pin 43 – Ground Connection:
This pin has some internal shielding function. It has to be
connected to ground.
Pin 44, 46, 48, 50, 52, 54 – Analog Outputs (Fig. 3–5):
These are the outputs of the six D/A converters. The D/A
converters are current source types and deliver output
currents from VSUPA to ground. The nominal output
voltages require 75 Ω load resistances. At higher load
resistances the output voltages will increase, but will be-
come nonlinear above approx. 2 V. The outputs are
short-circuit protected.
Pin 45 and 53 – Reference Resistors D/A Converters
(Fig. 3–6):
The reference currents for the D/A converters can be ad-
justed with a resistor from each of these pins to ground.
With these resistors the output currents can be adjusted
in the range of 25% to 100% of the maximal output cur-
rents. One resistor is responsible for the RGB D/A con-
verters, the other one for the Y,C,CVBS D/A converters.
11
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