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W65C21S Schematic ( PDF Datasheet ) - WDC

Teilenummer W65C21S
Beschreibung Peripheral Interface Adapter
Hersteller WDC
Logo WDC Logo 




Gesamt 16 Seiten
W65C21S Datasheet, Funktion
The Western Design Center, Inc.
W65C21S Data Sheet
www.DataSheet4U.com
Peripheral Interface Adapter (PIA)
W65C21S
The Western Design Center
W65C21S
1






W65C21S Datasheet, Funktion
The Western Design Center, Inc.
AC TIMING CHARACTERISTICS
W65C21S Data Sheet
www.DataSheet4U.com
Parameter
PHI2 Cycle
PHI2 Pulse Width
PHI2 Rise and Fall Time
READ TIMING
Parameter
Address Set-Up Time
Address Hold Time
Peripheral Data Setup Time
Data Bus Delay Time
Data Bus Hold Time
Symbol
tCYC
tC
trc tfc
14 MHz @ 5V
Min Max
70 -
35 -
-5
Unit
ns
ns
ns
Symbol
tACR
tCAR
tPCR
tCDR
tHR
14 MHz @ 5V
Min Max
10 -
0-
10 -
- 20
5-
Unit
ns
ns
ns
ns
ns
WRITE TIMING
Parameter
Address Set-Up Time
Address Hold Time
Data Bus Set-Up Time
Data Bus Hold Time
Peripheral Data Delay Time
Symbol
tACW
tCAW
tDCW
tHW
tCPW
14 MHz @ 5V
Min Max
10 -
0-
10 -
5-
- 20
Unit
ns
ns
ns
ns
ns
PERIPHERAL INTERFACE TIMING
Parameter
PHI2 Low to CA2 Low Delay
PHI2 Low to CA2 High Delay
CA1 Active to CA2 High Delay
PHI2 High to CB2 Low Delay
Peripheral Data Valid to CB2 Low
Delay
PHI2 High to CB2 High Delay
CB1 Active to CB2 High Delay
CA1, CA1, CB1, and CB2
Input Rise and Fall Time
Interrupt Input Pulse Width
Interrupt Response Time
Interrupt Clear Delay
Symbol
tCA2
tRS1
tRS2
tCB2
tDC
tRS1
tRS2
tr, tf
PWI
tRS3
tIR
14 MHz @ 5V
Min Max
- 20
- 20
- 25
- 70
5-
- 20
- 25
- 10
- 70
- 20
- 25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The Western Design Center
W65C21S
6

6 Page









W65C21S pdf, datenblatt
The Western Design Center, Inc.
that each interrupt request line services one peripheral data
port.
Each interrupt Request line has two interrupt flag bits that
can cause the Interrupt Request line to go low. These flags
are bits 6 and 7 in the two Control Registers (CRA, CRB).
These flags act as the link between the peripheral interrupt
signals and the microprocessor interrupt inputs. Each flag
has a corresponding interrupt disable bit which allows the
processor to enable or disable the interrupt from each of the
four interrupt inputs (CA1, CA2, CB1, CB2) The four
interrupt flags are set (enabled) by active transitions of the
signal on the interrupt input (CA1, CA2, CB1, CB2).
www.DataSheet4U.com
CRA bit 7 (IRQA1) is always set an active transition of the
CA1 interrupt input signal. However, IRQAB can be
disabled by setting bit 0 in CRA to a 0. Likewise, CRA bit 6
(IRQA2) can be set by an active transition of the CA2
interrupt input signal and IRQAB can be disabled by setting
bit 3 in CRA to a 0.
Both bit 6 and bit 7 in CRA are reset by a “Read Peripheral
Output Register A” operation. This is defined as an
operation in which the read/write, proper data direction
register and register select signals are provided to allow the
processor to read the Peripheral A I/O port. A summary of
IRQA control is shown in Table 3.
Control of IRQBB is performed in exactly the same manner
as that described above for IRQAB. Bit 7 in CRB (IRQB1)
is set by an active transition on CB1 and IRQBB from this
flag is controlled by CRB bit 0. Likewise, bit 6 (IRQB2) in
CRB is set by an active transition on CB2 and IRQBB from
this flag is controlled by CRB bit 3.
Also both bit 6 and bit 7 of CRB are reset by a “Read
Peripheral B Output Register” operation. A summary of
IRQBB control is shown in Table 3.
INTERRUPT STATUS CONTROL LOGIC (ISCA,
ISCB)
The four interrupt/peripheral control lines CA1, CA2, CB1,
CB2) are controlled by the Interrupt Status Control logic (A,
B). This logic interprets the contents of the corresponding
Control Register, thus allowing these lines to perform various
control functions as described in Figure 5.
PERIPHERAL I/O PORTS (PA0-PA7, PB0-PB7)
The Peripheral A and Peripheral B I/O ports allow the
microprocessor to interface to the input lines on a peripheral
device by writing data into the Peripheral Output Register.
They also allow the processor to interface with a peripheral
device’s output lines by reading the data on the Peripheral
Port input lines directly onto the data bus and into the internal
registers of the processor.
Each of the peripheral I/O lines can be programmed to act as
an input or an output. This is accomplished by setting a 1 in
the corresponding bit in the Data Direction Register for those
W65C21S Data Sheet
lines that are to act as outputs. A 0 in a bit of the Data
Direction Register causes the corresponding Peripheral I/O
lines to act as an input.
The buffers that drive the Peripheral A I/O lines each contain
two active pull-up transistors and one active pull-down
transistor. The pull-up transistors are resistive in nature and
therefore allow the output voltage to go to VCC for logic 1.
The pull down transistors can sink a full 3.2 mA, making
these buffers capable of driving two standard TTL loads.
In the input mode, the input pull-up transistors are connected
to the I/O pin and will supply enough current (100uA
minimum) to drive one standard TTL load.
When in the output mode Port A can drive with similar
current as the Port B buffers and can be thought of as push-
pull buffers. If Port A is clamped below 2.0V for a logic 1 or
above .8V for a logic 0 the data read during a read operation
may not correspond to the value wrote to the output registers.
This is a difference between the Port A buffers and the Port B
buffers and also is a difference with older versions of the
PIA.
The Peripheral B I/O port duplicates many of the functions of
the Peripheral A port. The process of programming these
lines to act as an input or an output is similar to the
Peripheral A port, as is the effect of reading or writing this
port. However, there are several characteristics of the buffers
driving these lines that affect their use in peripheral
interfacing.
The Peripheral B I/O buffers are push-pull devices, i.e., the
pull-up devices are switched OFF in the 0 state and ON for a
logic 1. Since these pull-ups are active devices, the logic 1
voltage will go to the VDD power supply level.
Another difference between the PA0-PA7 lines and the PBO
through PB7 lines is that they have three-state capability
which allows them to enter a high impedance state when
programmed to be used as input lines. In addition, data on
these lines will be read properly, when programmed as output
lines, even if the data signals fall below 2.0 volts for a “high”
state or are above 0.8 volts for a “low” state. When
programmed as output, each line can drive at least two TTL
load and may also be used as a source of up to 3.2 mA at 1.5
volts to directly drive the base of a transistor switch, such as
a Darlington pair. A limiting resistor should be used to
prevent excessive current when clamping an output on the
PIA.
Because these outputs are designed to drive transistors
directly, the output data is read directly from the Peripheral
Output Register for those lines programmed to act as inputs.
The final characteristic is the high-impedance input state
which is a function of the Peripheral B push-pull buffers.
When the Peripheral B I/O lines are programmed to act as
inputs, the output buffer enters the high impedance state. All
pins are read when in the input mode.
PERIPHERAL OUTPUT REGISTERS (ORA, ORB)
The Western Design Center
W65C21S
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