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PDF PCLT-2A Data sheet ( Hoja de datos )
| Número de pieza | PCLT-2A | |
| Descripción | Dual current limited over-voltage protected digital termination | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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PCLT-2A
Dual current limited over-voltage protected digital termination
Applications
■ Type 1, 2 and 3 logic input termination for
www.DataSheet4U.comindustrial automation
■ AS-Interface bus input termination
■ I/O termination in programmable logic
controller
■ Proximity detector interface
■ Decentralized Input / Output modules
Features
■ 2 channel topology
– Low side input with common ground
■ Wide range input DC Voltage:
– VI = - 0.3 to 30 V with RI = 0 Ω
– VI = - 30 to 35 V with RI = 750 Ω
■ Current limiter:
– 3 to 7.5 mA programmable reference
– ILIM = 6.1 mA to 8.8 mA with RREF = 10 kΩ
– ILIM = 2.8 mA to 4.3 mA with RREF = 22 kΩ
– Narrow limiter spread: < 17 %
– Temperature compensated operation
■ Output drive:
– No output activation below 2 mA input
current
– 1.5 mA minimum output activating current
in opto-coupler mode
– Programmable CMOS output mode option
(VMOD > 2.9 V)
■ LED drive for sensor status: 4.4 mA typical with
RREF = 10 kΩ
■ Input protection (RI = 750 Ω CIN = 22 nF)
■ IEC61000-4-2 electrostatic discharge ESD,
Level 4
– In contact, ± 8 kV; in air, ± 15 kV
– Criteria B: temporary disruption
November 2005
TSSOP14
Exposed pad
■ IEC61000-4-5 voltage surge, Level 3
– ± 500 V with 42 Ω series resistor in
differential mode
– Criteria B: temporary disruption
■ IEC61000-4-4 transient burst immunity
– ± 4 kV peak voltage; 5 kHz repetitive rate
– Criteria A: fully functional
■ IEC61000-4-6 conducted Radio Frequency
Interference immunity
– 10 VRMS voltage
– Criteria A: fully functional
■ Input protection against -30 V reverse polarity
■ Ambient temperature: -25 to 85 °C
Benefits
■ Enable input to meet type1, 2 and 3
characteristics of IEC61131-2 standard
■ Compatible operation with 2 & 3 wires
proximity sensor according EN60947-5-2
standard
■ Flexible configuration driving either opto
coupler, or CMOS bus controller input, or 12 V
AS-interface network
■ Reduced overall dissipation
■ Enhanced functional reliability
■ Compact with high integration
■ Surface Mount Package for highly automated
assembly
■ Insensitive to the on state sensor impedance
Rev 1
1/18
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18
1 page  
PCLT-2A
1 Characteristics
1.6 Electromagnetic compatibility ratings
TJ=25 °C, RI = 750 Ω RC = 2.2 kΩ , & reverse diode connected (unless otherwise specified)
Symbol Node Parameter name & conditions
Value
Unit
VESD
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VPPB
VPP
VPP
VPP
ESD protection, IEC 61000-4-2, per input, in air
IN ESD protection, IEC 61000-4-2, per input, in contact
VCC ESD protection, IEC 61000-4-2, per input, in air, RI = 0 Ω
ESD protection, IEC 61000-4-2, per input, in contact, RI = 0 Ω
VI
Total Peak Pulse Voltage Burst, IEC61000-4-4
CC = 33 nF, CI = 22 nF, F = 5 kHz (Note 1)
VI Peak Pulse Voltage Surge, IEC61000-4-5, R = 42 Ω (Note 2)
VI Peak Pulse Voltage Surge, IEC61000-4-5, R = 42 Ω RI = 1200 Ω (Note 2)
VCC Peak Pulse Voltage Surge, IEC61000-4-5, R = 2 Ω (Note 2)
± 15
±8
±3
±3
±4
± 500
± 1000
± 1000
kV
kV
kV
kV
kV
V
V
V
Note: 1 Test diagram described on Figure 1 using the application PCB with a normalized capacitive
coupling clamp
2 Test diagram described on Figure 1
1.7 Thermal resistance
Symbol
Parameter name & conditions
RTH JA
Thermal resistance Junction to ambient
Board copper surface = 1.25 cm², copper thickness = 35 µm, single face
Value
Unit
100 °C/W
5/18
5 Page 
PCLT-2A
3 Surge voltage test circuit
2.3
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ON state
When the module input voltage VI, including the 750 Ω input resistor and the reverse diode, is
higher than 11V corresponding to a PCLT input voltage VIN of 5V, both LED and output circuits
are in ON state. The input current is then shared between the internal circuitry, the LED (about
60 %), and the driver output (about 30 %) in case of opto-coupler mode.
In CMOS mode, the CMOS level is defined by the VMOD voltage that is equal the supply voltage
VDD of the bus controller: it can be 3.3 V or 5 V. The output voltage is delivering 80 % of VDD for
high state and 20 % VDD for low state.
When no LED diode is used, the LED outputs pin must be connected to the ground COMP of
the circuit to allow the current to flow back to the power supply.
3 Surge voltage test circuit
The input and supply pins are designed to withstand electromagnetic interferences. They are
protected by a clamping diode that is connected to the common pin COM. Combined with the
serial input resistance RI, this clamping diode is effective against the fast transient bursts (±4
kV, IEC61000-4-4) and the voltage surges (±1 kV,IEC61000-4-5).
This topology allows the surge voltage to be applied from each input to other inputs, the ground
and the supply contacts in differential or common modes (see figure 10).
Thanks to its high resistance RC = 2.2 kΩ and the conventional power supply protection that
uses a clamping diode such as the SM15T39C Transil™, the supply pin VC withstands ±1000 V
surge voltage according to IEC61000-4-5 (see figure 11).
Figure 10. Input pin IN voltage surge test
circuit
VPP = ±500 V with 42 Ω
VPP
I
VPP
VPP
GND
PE/FE
5 nF
VCC
RC
RI
RI
RI
VC PCLT -2
IN1
IN2
COMP
Figure 11. Supply pin VC voltage surge test
circuit
VCC
±1kV
2Ω
±1 kV
42 Ω
GND
PE/FE
SM15T39C
5 nF
RC VC PCLT -2
RI
IN1
RI
IN2
COM
TM: Transil is a trademark of STMicroelectronics
11/18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet PCLT-2A.PDF ] | |
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