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PDF AKD5702-A Data sheet ( Hoja de datos )
| Número de pieza | AKD5702-A | |
| Descripción | portable digital audio 16bit A/D converter | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AKD5702-A]
AKD5702-A
AK5702 Evaluation Board Rev.1
GENERAL DESCRIPTION
AKD5702-A is an evaluation board for the portable digital audio 16bit A/D converter with MIC-AMP,
AK5702. AKD5702-A also has the digital audio interface and can achieve the interface with digital audio
systems via opt-connector.
Ordering guide
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AKD5702-A
--- AK5702 Evaluation Board
(Cable for connecting with printer port of IBM-AT compatible PC and control software
are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT with optical output
• BNC connector for an external clock input
• 10pin Header for serial control interface
AVDD DVDD VD AGND DGND
5V 3.0V
Regulator
Control Data
10pin Header
LIN3/4/5
MIC3/4/5
RIN3/4/5
LIN1/2/5
MIC1/2/5
RIN1/2/5
AK5702
EXT_MCLK
EXT_LRCK
EXT_BCLK
CLOCK
GEN
AK4114
(DIT)
DSP 1
10pin Header
TDM
10pin Header
DSP 2
10pin Header
Opt In
Opt Out
Figure 1. AKD5702-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM086501>
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ASAHI KASEI
c) Set up jumper pins of LRCK clock
JP11
LRCKFS
JP13
LRCK_SEL
[AKD5702-A]
d) Set up jumper pins of SDTO
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JP30
SDTO_SEL
JP29
SDTOB
AB
(2-a) In the case of using AK4114.
* In this mode, MCLK of AK5702 should be supplied from J1 (EXT_MCKI), and X1 should be open.
This mode is BCLK=64fs, LRCK=1fs only.
Set up jumper pins of MCKI clock
JP16
XTI
JP7
MCKI_SEL
JP5
TDMMCLK_SEL
JP32
MCLK_SEL
JP8
MKFS
MCKO EXT_MCLK DIT
EXT
MCKO EXT_MCLK
*The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So
JP8(MKFS) should set up any.
Set up jumper pins of BCLK clock
JP28
M/S
JP9
BCLKFS
JP10
BCLK_SEL
MS
Set up jumper pins of LRCK clock
JP11
LRCKFS
JP13
LRCK_SEL
<KM086501>
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2007 / 04
5 Page 
ASAHI KASEI
[AKD5702-A]
Other jumper pins set up
1. JP1, JP3 (MPWRB): Connect to MPWRB
OPEN
: No connect <Default>
SHORT
: Connect to MPWRB
2. JP2, JP4 (MPWRA) : Connect to MPWRA
OPEN
: No connect <Default>
SHORT
: Connect to MPWRA
3. JP17 (LIN125_SEL)
LIN1
LIN2
LIN5
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4. JP18 (RIN125_SEL)
RIN1
RIN2
RIN5
: Select input pin from J4
: Enable to input to LIN1 from J4 <Default>
: Enable to input to LIN2 from J4
: Enable to input to LIN5 from J4
: Select input pin from J6
: Enable to input to RIN1 from J6 <Default>
: Enable to input to RIN2 from J6
: Enable to input to RIN5 from J6
5. JP19 (LIN5_SEL)
LIN125
LIN345
: Select input connecter to LIN5
: Enable to input to LIN5 from J4 <Default>
: Enable to input to LIN5 from J7
6. JP20 (RIN5_SEL)
RIN125
RIN345
: Select input connecter to RIN5
: Enable to input to RIN5 from J6 <Default>
: Enable to input to RIN5 from J9
7. JP21 (LIN345_SEL)
LIN3
LIN4
LIN5
: Select input pin from J7
: Enable to input to LIN3 from J7 <Default>
: Enable to input to LIN4 from J7
: Enable to input to LIN5 from J7
8. JP22 (RIN345_SEL)
RIN3
RIN4
RIN5
: Select input pin from J9
: Enable to input to RIN3 from J9 <Default>
: Enable to input to RIN4 from J9
: Enable to input to RIN5 from J9
9. JP35 (SDTOB_SEL) : Select input pin to TDMIN
PDOWN
: Connect to GND <Default>
SDTOB
: Connect to SDTOB
10. JP36 (CTRL_SEL) : Select for µp Control Mode
3-WIRE : Select to 3-WIRE <Default>
I2C : Select to I2C
11. JP37 (GND)
OPEN
SHORT
: Analog ground and Digital ground
: Separated. <Default>
: Common. (The connector “DGND” should be open.)
12. JP38 (AVDD_SEL) : AVDD of the AK5702
REG
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD
: AVDD is supplied from “AVDD ” jack.
<KM086501>
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11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet AKD5702-A.PDF ] | |
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