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DS1685 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS1685
Beschreibung (DS1685 / DS1687) 3V/5V Real-Time Clocks
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 33 Seiten
DS1685 Datasheet, Funktion
www.DataSheet4U.com
www.maxim-ic.com
FEATURES
Incorporates Industry-Standard DS1287 PC Clock
plus Enhanced Features Such as:
§ Y2K Compliant
§ +3V or +5V Operation
§ 64-Bit Silicon Serial Number
§ Power-Control Circuitry Supports System Power-
On from Date/Time Alarm or Key Closure
§ 32kHz Output for Power Management
§ Crystal-Select Bit Allows RTC to Operate with
6pF or 12.5pF Crystal
§ SMI Recovery Stack
§ 242 Bytes Battery-Backed NV RAM
§ Auxiliary Battery Input
DS1685/DS1687
3V/5V Real-Time Clocks
§ RAM Clear Input
§ Century Register
§ Date Alarm Register
§ Compatible with Existing BIOS for Original
DS1287 Functions
§ Available as Chip (DS1685) or Stand-Alone
Encapsulated DIP (EDIP) with Embedded
Battery and Crystal (DS1687)
§ Timekeeping Algorithm Includes Leap-Year
Compensation Valid Through 2099
§ Underwriters Laboratory (UL) Recognized
APPLICATIONS
Embedded Systems
Utility Meters
Security Systems
Network Hubs, Bridges, and Routers
PIN CONFIGURATIONS
TOP VIEW
PWR
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1 24
2 DS1685/ 23
3 DS1685S/ 22
4 DS1685E 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
SQW
VBAUX
RCLR
VBAT
IRQ
KS
RD
GND
WR
ALE
CS
DIP (0.600”)/
SO (0.300”)/
TSSOP (0.173”)
PACKAGE DIMENSION
INFORMATION
www.maxim-ic.com/DallasPackInfo
AD0
AD1
AD2
AD3
AD4
AD5
N.C.
4 3 2 1 28 27 26
5 25
6
7
DS1685Q
24
23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
RCLR
VBAT
IRQ
KS
RD
GND
WR
PLCC
PWR
N.C.
N.C.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2 DS1687
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
EDIP (740 mil)
VCC
SQW
VBAUX
RCLR
N.C.
IRQ
KS
RD
N.C.
WR
ALE
CS
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 032604






DS1685 Datasheet, Funktion
www.DataSheet4U.com
Figure 1. Block Diagram
DS1685/DS1687 3V/5V Real-Time Clocks
DS1687 only
X1
OSC
X2
VCC
GND
VBAUX
VBAT
Power
Control
DS1687 only
CS
RD
WR
ALE
BUS
Interface
AD0 - AD7
Divide
by 8
Divide by
64
Divide by
64
Clock/Calender
Update Logic
16:1 Mux
Square
Wave
Generator
IRQ
Generator
Registers A, B,C,D
Clock/Calendar and
Alarm Registers
Buffered Clock/
Calendar and Alarm
Registers
User Ram
114 Bytes
RAM
Clear
Logic
SQW
IR Q
PWR
KS
RLCR
Select
DS1685/DS1687
Extended RAM Addr/
Data Registers
Extended Control/
Status Registers
64-Bit Serial Number
Century Counter
Date Alarm
RTC Address -2
RTC Address -3
Extended
User RAM
128 Bytes
OSCILLATOR CIRCUIT
The DS1685 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 1 specifies several crystal parameters for the external crystal, and Figure 2 shows a
functional schematic of the oscillator circuit. The oscillator is controlled by an enable bit in the control register.
Oscillator startup times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR
and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the
recommended characteristics and proper layout usually starts within one second.
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DS1685 pdf, datenblatt
www.DataSheet4U.com
Register B (0Bh)
MSB
BIT 7
BIT 6
SET PIE
BIT 5
AIE
BIT 4
UIE
DS1685/DS1687 3V/5V Real-Time Clocks
BIT 3
SQWE
BIT 2
DM
BIT 1
24/12
LSB
BIT 0
DSE
SET – When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second.
When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize the time and
calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar
manner. SET is a read/write bit that is not modified by internal functions of the DS1685/DS1687.
PIE – The periodic-interrupt enable bit is a read/write bit that allows the periodic-interrupt flag (PF) bit in Register C
to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated by driving the IRQ pin low at
a rate specified by the RS3–RS0 bits of Register A. A 0 in the PIE bit blocks the IRQ output from being driven by a
periodic interrupt, but the periodic flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal
DS1685/DS1687 functions.
AIE – The alarm-interrupt enable (AIE) bit is a read/write bit which, when set to a 1, permits the alarm flag (AF) bit
in Register C to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three
alarm bytes, including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is set to 0, the AF bit does
not initiate the IRQ signal. The internal functions of the DS1685/DS1687 do not affect the AIE bit.
UIE – The update-ended interrupt-enable (UIE) bit is a read/write bit that enables the update-end flag (UF) bit in
Register C to assert IRQ. The SET bit going high clears the UIE bit.
SQWE – When the square-wave enable (SQWE) bit is set to a 1 and E32K = 0, a square-wave signal at the
frequency set by the rate-selection bits RS3–RS0 is driven out on the SQW pin. When the SQWE bit is set to 0 and
E32K = 0, the SQW pin is held low. SQWE is a read/write bit.
DM – The data mode (DM) bit indicates whether time and calendar information is in binary or BCD format. The DM
bit is set by the program to the appropriate format and can be read as required. This bit is not modified by internal
functions. A 1 in DM signifies binary data while a 0 in DM specifies BCD data.
24/12 – The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and a 0
indicates the 12-hour mode. This bit is read/write.
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit that enables two daylight savings adjustments
when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last
Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. When DSE is enabled, the
internal logic tests for the first/last Sunday condition at 1:59:59 AM. If the DSE bit is not set when the test occurs,
the daylight savings function will not operate correctly. These adjustments do not occur when the DSE bit is a
zero. This bit is not affected by internal functions.
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