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ADC0804 Schematic ( PDF Datasheet ) - Harris

Teilenummer ADC0804
Beschreibung (ADC0802 - ADC0804) 8-Bit/ Microprocessor- Compatible/ A/D Converters
Hersteller Harris
Logo Harris Logo 




Gesamt 16 Seiten
ADC0804 Datasheet, Funktion
www.DataSheet4U.com
Semiconductor
August 1997
ADC0802, ADC0803
ADC0804
8-Bit, Microprocessor-
Compatible, A/D Converters
Features
Description
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time < 100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required
The ADC0802 family are CMOS 8-Bit, successive-approxi-
mation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Ordering Information
PART NUMBER
ADC0802LCN
ADC0802LCD
ADC0802LD
ADC0803LCN
ADC0803LCD
ADC0803LCWM
ADC0803LD
ADC0804LCN
ADC0804LCD
ADC0804LCWM
ERROR
±1/2 LSB
±3/4 LSB
±1 LSB
±1/2 LSB
±3/4 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 = 2.500VDC (No Adjustments)
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
PKG. NO
E20.3
F20.3
F20.3
E20.3
F20.3
M20.3
F20.3
E20.3
F20.3
M20.3
Pinout
Typical Application Schematic
ADC0802, ADC0803, ADC0804
(PDIP, CERDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
ANY
µPROCESSOR
1 CS
2 RD
V+ 20
CLK R 19
+5V 150pF
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
VREF/2
DGND
6
7
8
9
10
DIFF
INPUTS
VREF/2
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
6-5
File Number 3094.1






ADC0804 Datasheet, Funktion
www.DataSheet4U.com
ADC0802, ADC0803, ADC0804
Typical Performance Curves
1.8
-55oC TO 125oC
1.7
1.6
1.5
1.4
500
400
300
200
1.3
4.50
4.75
5.00
5.25
V+ SUPPLY VOLTAGE (V)
5.50
FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY
VOLTAGE
100
0
200 400 600 800
LOAD CAPACITANCE (pF)
1000
FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT
DATA VALID vs LOAD CAPACITANCE
3.5
3.1 VT(+)
2.7
-55oC TO 125oC
2.3
1.9
VT(-)
1.5
4.50
4.75
5.00
5.25
V+ SUPPLY VOLTAGE (V)
5.50
FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY VOLTAGE
7
6 V+ = 4.5V
5
4
3
2 V+ = 5V
1
0 V+ = 6V
0
400
800
1200
1600
2000
fCLK (kHz)
FIGURE 6. FULL SCALE ERROR vs fCLK
1000
R = 50K
R = 10K
R = 20K
100
10
100
CLOCK CAPACITOR (pF)
FIGURE 5. fCLK vs CLOCK CAPACITOR
1000
16
VIN(+) = VIN(-) = 0V
14 ASSUMES VOS = 2mV
THIS SHOWS THE NEED
12 FOR A ZERO ADJUSTMENT
IF THE SPAN IS REDUCED
10
8
6
4
2
0
0.01
0.1 1.0
VREF/2 (V)
5
FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR
6-10

6 Page









ADC0804 pdf, datenblatt
www.DataSheet4U.com
ADC0802, ADC0803, ADC0804
150pF
N.O.
START
ANALOG
INPUTS
10K
ADC0802 - ADC0804
1 CS
V+ 20
2 RD CLK R 19
3 WR
4 CLK IN
5 INTR
6 VIN (+)
7 VIN (-)
8 AGND
9 VREF/2
10 DGND
DB0 18
DB1 17
DB2 16
DB3 15
DB4 14
DB5 13
DB6 12
DB7 11
5V (VREF)
+
10µF
LSB
DATA
OUTPUTS
MSB
FIGURE 17. FREE-RUNNING CONNECTION
Driving the Data Bus
This CMOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuItry, which is tied to the data
bus, will add to the total capacitive loading, even in three-
state (high-impedance mode). Back plane busing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to han-
dle this problem. Basically, the capacitive loading of the data
bus slows down the response time, even though DC specifi-
cations are still met. For systems operating with a relatively
slow CPU clock frequency, more time is available in which to
establish proper logic levels on the bus and therefore higher
capacitive loads can be driven (see Typical Performance
Curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock-extending circuits (6800).
Finally, if time is short and capacitive loading is high,
external bus drivers must be used. These can be three-state
buffers (low power Schottky is recommended, such as the
74LS240 series) or special higher-drive-current products
which are designed as bus drivers. High-current bipolar bus
drivers with PNP inputs are recommended.
Power Supplies
Noise spikes on the V+ supply line can cause conversion
errors as the comparator will respond to this noise. A
low-inductance tantalum filter capacitor should be used
close to the converter V+ pin, and values of 1µF or greater
are recommended. If an unregulated voltage is available in
the system, a separate 5V voltage regulator for the converter
(and other analog circuitry) will greatly reduce digital noise
on the V+ supply. An lCL7663 can be used to regulate such
a supply from an input as low as 5.2V.
Wiring and Hook-Up Precautions
Standard digital wire-wrap sockets are not satisfactory for
breadboarding with this A/D converter. Sockets on PC
boards can be used. All logic signal wires and leads should
be grouped and kept as far away as possible from the analog
signal leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup; therefore, shielded
leads may be necessary in many applications.
A single-point analog ground should be used which is separate
from the logic ground points. The power supply bypass capaci-
tor and the self-clockIng capacitor (if used) should both be
returned to digital ground. Any VREF/2 bypass capacitors, ana-
log input filter capacitors, or input signal shielding should be
returned to the analog ground point. A test for proper grounding
is to measure the zero error of the A/D converter. Zero errors in
excess of 1/4 LSB can usually be traced to improper board
layout and wiring (see Zero Error for measurement). Further
information can be found in Application Note AN018.
Testing the A/D Converter
There are many degrees of complexity associated with testing
an A/D converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs to
display the resulting digital output code as shown in Figure 18.
For ease of testing, the VREF/2 (pin 9) should be supplied
with 2.560V and a V+ supply voltage of 5.12V should be
used. This provides an LSB value of 20mV.
If a full scale adjustment is to be made, an analog input volt-
age of 5.090V (5.120 - 11/2 LSB) should be applied to the
VIN(+) pin with the VIN(-) pin grounded. The value of the
VREF/2 input voltage should be adjusted until the digital out-
put code is just changing from 1111 1110 to 1111 1111. This
value of VREF/2 should then be used for all the tests.
The digital-output LED display can be decoded by dividing the 8
bits into 2 hex characters, one with the 4 most-significant bits
(MS) and one with the 4 least-significant bits (LS). The output is
then interpreted as a sum of fractions times the full scale voltage:
VO UT = M--1---6-S-- + 2--L--5-S--6--(5.12)V .
10k
150pF
N.O.
START
VIN (+) 0.1µF
AGND
2.560V
VREF/2
0.1µF
1
2
3
4
5 ADC0802-
6 ADC0804
7
8
9
10
DGND
20 + 5.120V
10µF
19 TANTALUM
18 LSB
17
16
15
5V
14
13
12
11 MSB
1.3kLEDs
(8) (8)
FIGURE 18. BASIC TESTER FOR THE A/D
For example, for an output LED display of 1011 0110, the
MS character is hex B (decimal 11) and the LS character is
hex (and decimal) 6, so:
VO UT = 11----16-- + 2----65---6--(5.12) = 3.64V.
6-16

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