GD16585 Datasheet PDF - Giga
| Part Number | GD16585 | |
| Description | (GD16585 / GD16589) Transmitter MUX | |
| Manufacturers | Giga | |
| Logo |  |
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www.DataSheet4U.com
an Intel company
10 Gbit/s
Transmitter MUX
with Re-timing
GD16585/GD16589
(FEC)
Preliminary
General Description
Features
GD16585 and GD16589 are transmitter
chips used in SDH STM-64 and SONET
OC-192 optical communication systems.
The device is available in two versions:
u GD16585 for 9.5328 Gbit/s.
u GD16589 for 10.66 Gbit/s with
Forward Error Correction (FEC).
Except the different operating bit rate the
two versions are functional identical.
The transmitter integrates the main func-
tions of the serializer which are:
u Clock Multiply Unit (CMU)
u 16:1 Multiplexer in a single monolithic
IC.
The CMU consists of Phase Locked
Loop (PLL) controlled from an external
reference clock. The PLL characteristics
are controlled by an external loop filter al-
lowing the user to optimize the jitter
perfomance of the device.
The 16:1 Multiplexer accepts 16 parallel
input bits at 622.88 Mbit/s (or 666 Mbit/s)
that are serialized into a 9.9538 Gbit/s (or
10.66 Gbit/s) data stream. The serialized
data stream is re-timed by the high-
speed clock from the VCO.
The parallel input interface features
GIGA’s unique self-synchronizing dy-
namic phase alignment scheme that al-
lows both:
u Source synchronous counter clocking
for OIF99.102.5 interfaces.
u Forward clocking with phase nulling
and jitter clean-up of the clock.
These schemes enable the serializer to
absorb output delay variations from the
upstream System ASIC without use of
initialization or reset.
The data and clock inputs to the MUX
are LVDS and the output data is CML
compatible.
The device operates from a dual -5.2 V
and +3.3 V power supply. The power dis-
sipation is 2.2 W, typical.
The device is manufactured in a Silicon
Bipolar process and packaged in an 132
balls 13 × 13 mm Ceramic/Plastic Ball
Grid Array (CBGA).
DI0
DIN0
Parallel
Input Data
DI15
DIN15
16:1
Multiplexer
SEL1
SEL2
CKOUT
CKOUTN
CKI
CKIN
Phase
Selector
PFCX
FF
Timing
Control
VCO
Phase
Frequency
Detector
VCUR
OUT
OUTN
VCTL
PCTL
(PHIGH)
(PLOW)
NLDET
PCTLX SGNX
TCK
SEL3 REFCK/N VCC VDD VDDO VDDA VEE
l PLL based CMU with on-chip 10 GHz
or 10.66 GHz VCO.
l 16:1 Multiplexer with a last stage
re-timing.
l OIF99.102.5 compliant timing .
l LVDS compatible parallel data and
clock inputs
l CML compatible serial data output.
l 155 MHz or 622 MHz reference clock
input (selectable).
l Divide by 16 clock output.
l PLL out of lock detector.
l Dual supply operation: -5.2 V and
+3.3 V
l Low power dissipation: 2.2 W (typ.).
l Available in three package versions:
– EB: 132 ball (16 mill) Ceramic
BGA 13 × 13 mm
– EF: 132 ball (20 mill) Ceramic
BGA 13 × 13 mm
– FB: 132 ball (20 mill) Plastic
BGA 13 × 13 mm
l
l Available in two versions:
– GD16585 for 10 Gbit/s
– GD16589 for 10.66 Gbit/s
Applications
l Telecommunication systems:
– SDH STM-64
– SONET OC-192
– Optical Transport Networking
(OTN)
– FEC applications
l Fibre optic test equipment.
Data Sheet Rev.: 13
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10 Gbit/s Output Interface
www.DataSheet4U.com
GD16585/GD16589
0V
50W
OUT
OUTN
50W MSL
-5.2V
VCUR
Figure 3. 10 Gbit/s outputs (OUT/OUTN), DC coupled.
Driver
50W
GD16585/GD16589
0V
50W
OUT
100nF
OUTN
50W MSL
Driver
50W
-5.2V
VCUR
Figure 4. 10 Gbit/s outputs (OUT/OUTN), AC coupled.
Note: With AC coupled outputs VCUR must not be connected directly to 0 V.
Data Sheet Rev.: 13
GD16585/GD16589
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for GD16585 electronic component. |
| Information | Total 17 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ GD16585.PDF Datasheet ] | |
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