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CD40xxB Schematic ( PDF Datasheet ) - Harris Semiconductor

Teilenummer CD40xxB
Beschreibung (CD4000B Series) Technical Overview
Hersteller Harris Semiconductor
Logo Harris Semiconductor Logo 




Gesamt 16 Seiten
CD40xxB Datasheet, Funktion
www.DataSheet4U.com
Technical Overview
CD4000B Series
This section is intended as a guide for circuit and equipment
designers in the operation and application of MOS inte-
grated circuits. It covers general operating and handling con-
siderations with respect to the following critical factors:
• Operating Supply Voltage Range
• Power Dissipation and Derating
• System Noise Considerations
• Power Source Rules
• Gate-oxide Protection Networks
• Input Signals and Ratings
• Chip Assembly and Storage
• Device Mounting
• Testing
More specific information is then given on significant fea-
tures, special design and application requirements, and
standard ratings and electrical characteristics for CMOS B-
series logic circuits, and on CMOS special function circuits
(special interface and display driver circuits).
General Operating and Handling
Considerations
The following paragraphs discuss some key operating and
handling considerations that must be taken into account to
achieve maximum advantage of the CMOS technology.
Additional information on the operation and handling of
CMOS integrated circuits is given in Application Note
AN6525, “Guide to Better Handling and Operation of CMOS
Integrated Circuits”. See Section 8, “How to Use Answer-
FAX”, in this selection guide.
Operating Supply Voltage Range
Because logic systems occasionally experience transient con-
ditions on the power supply line which, when added to the
nominal power-bus voltage, could exceed the safe limits of cir-
cuits connected to the power bus, the recommended operat-
ing supply voltage range is 3V to 18V for B-series devices.
The recommended maximum power supply limit is substan-
tially below the minimum primary breakdown limit for the
devices to allow for limited power supply transient and regula-
tion limits. For circuits that operated in a linear mode over a
portion of the voltage range, such as RC or crystal oscillators,
a minimum supply voltage of 4V is recommended.
Power Dissipation and Derating
The power dissipation of a CMOS integrated circuit is the
sum of a DC (quiescent) component and an AC (dynamic)
components. The DC component is the sum of the net inte-
grated circuit reverse diode junction current and the surface
leakage current times the supply voltage. In standard B-
series logic devices, the DC dissipation typically ranges,
depending upon device complexity, from 100nW to 400nW
for a supply voltage of 10V. Worst-case DC dissipation is the
product of the maximum quiescent current (given in the data
sheet on each device) and the DC supply voltage VDD.
Dynamic power dissipation has three components:
1. The dissipation that results from current that charges and
discharges the external load capacitance of the output
buffers. The dissipation of each output buffer is equal to
CV2f, where C is the load capacitance, V is the supply
voltage, and f is the switching frequency of that output.
2. The dissipation that results from current that charges and
discharges the internal node capacitances.
3. The dissipation caused by the current spikes through the
PMOS and NMOS transistors in series at the instant of
switching. This component amounts to approximately
10% of the total dissipation, shown graphically in the
datasheets of most CMOS circuits.
All CMOS devices are rated at 200mW per package at the
maximum operating ambient temperature rating (TA) of
125oC for all packages. Power ratings for temperatures
below the maximum operating temperature are shown in the
standard CMOS thermal derating chart in Figure 1. This
chart assumes that the device is mounted and soldered (or
placed in a socket) on a PC board; there is natural convec-
tion cooling, with the PC board mounted horizontally; and
the pressure is standard (14.7psia). In addition to the overall
package dissipation, device dissipation per output transistor
is limited to 100mW maximum over the full package operat-
ing temperature range.
SLOPE = 12mW/oC
600
500
400
300
200
100
20 40 60 80 85 100
TA, AMBIENT TEMPERATURE (oC)
120 125
FIGURE 1. STANDARD CMOS THERMAL DERATING CHART
System Noise Considerations
In general, CMOS devices are much less sensitive to noise
on power and ground lines than bipolar logic families (such
as TTL or DTL). However, this sensitivity varies as a function
of the power supply voltage, and more importantly as a func-
tion of synchronism between noise spikes and input transi-
tions. Good power distribution in digital systems requires
that the power bus have a low dynamic impedance; for this
purpose, discrete decoupling capacitors should be distrib-
uted across the power bus. A more detailed discussion of
CMOS noise immunity is provided by Application Note
AN6587, “Noise Immunity of B-series CMOS Integrated Cir-
cuits”. See Section 8, “How to Use AnswerFAX”, in this
selection guide.
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CD40xxB Datasheet, Funktion
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Technical Overview
characteristics of B-series CMOS integrated circuits. The
JEDEC standard (JEDEC Tentative Standard No. 13B)
defines B-series CMOS integrated circuits as a uniform fam-
ily of both buffered and unbuffered types that have an abso-
lute DC supply voltage rating of at least 18V.
Buffered CMOS Devices
These are types in which the output “on” impedance is inde-
pendent of any and all valid input logic conditions, both pre-
ceding and present. All such CMOS products are designated
by suffix “B” following the basic type number.
• Tight Limits For All Packages
Harris devices used the same set of limits for all package
styles. The JEDEC standard establishes two sets of limits
for most DC parameters; a tight set for products having a
full operating temperature range of -55oC to +125oC (all
Harris devices), and a relaxed set for products having a
limited temperature range of -40oC to +85oC. Because
Harris supplies only one premium grade of B-series prod-
uct in all package styles (i.e., fall-out chips are not used),
all B-series CMOS devices are specified to the tight set of
limits only.
Unbuffered CMOS Devices
These are types that meet all B-series specifications except
that the logical outputs are not buffered and the noise-immu-
nity voltages, VIL and VIH, are specified as 20% and 80%,
respectively, of VDD for operation from 5V, 10V, and 17V and
83%, respectively, of VDD for operation from 15V. All such
CMOS product are designated by the suffix “UB”.
• Improved Voltage Rating
All Harris B-series devices are tested to voltages that
insure safe operation at the absolute maximum DC supply
voltage rating of 20V. This higher rating permits greater
derating for reliable 15V operation, permits greater 15V
supply tolerance and peak transients, and permits system
use to 18V with confidence.
The JEDEC minimum standard also includes in the B-series,
CMOS types that have analog inputs or outputs and in addi-
tion, have maximum ratings and logical input and output
parameters that conform to B-series specifications wherever
applicable. These CMOS devices are also designated by the
suffix “B”.
• Wider Operating Range
All Harris B-series devices have a recommended maxi-
mum operating voltage of 18V. The higher limit permits
18V system supply operation, and also permits wider
power source tolerance and transients for supplies nor-
mally set up to 18V
All B-series CMOS devices can directly replace their A-series
counterparts in most applications. The UB types are high volt-
age versions of corresponding A-series (unbuffered) types.
Commercial A-series types have been obsoleted and
replaced by B-series counterparts with only a few exceptions
such as the continuing CD4059A types.
The Absolute Maximum Rating - JEDEC table lists the
minimum standards established for the maximum ratings
and recommended operating conditions for B-series CMOS
integrated circuits.
• Lower Leakage Current
The JEDEC standard establishes three sets of limits for
quiescent device current (IDD) intended to match chip
complexity to device leakage current as realistically as
possible.
For all three levels of chip complexity, all Harris B-series
devices (regardless of package) conform to the tighter set
of limits established in the standard. In addition, a maxi-
mum rating is specified at 20V, as well as at 5V, 10V, and
15V. As a result:
The DC Electrical Specification - JEDEC table shows the
JEDEC standards for the DC electrical specifications of
CMOS B-series integrated circuits.
- In current limited applications, CMOS users can depend
on one tight leakage limit independent of package style
selected.
Standardized Ratings and Static Characteristics
Harris B-series CMOS integrated circuits meet or exceed the
most stringent requirements of the JEDEC B-series specifi-
cations. The Absolute Maximum Ratings table shows the
standardized maximum ratings and recommended operating
supply voltage range for Harris B-series CMOS integrated
circuits. The standardized DC electrical specifications for
these devices are shown in the DC Electrical Specification
table. As with the JEDEC specifications, the Harris standard-
ized characteristics classify the B-series devices into three
leakage (quiescent device current) categories. Table 1 lists
the Harris types in each category and indicates types that,
although they are still B-series types, differ in one or more
static characteristics.
The Absolute Maximum Ratings table and the DC Electri-
cal Specification table show that in a number on important
respects, Harris has established new performance stan-
dards for B-series CMOS logic circuits.
- Customer use of CMOS product up through 18V is pro-
tected by a published tight leakage current specification at
20V (as well as by an input leakage specification at 18V).
• Symmetrical Output
Most Harris B-series devices have balanced complemen-
tary output drive (i.e., the output high current IOH rating is
the same as the output low current IOL rating specified to
the tighter set of limits established in the JEDEC standard.
The balanced output provides uniform rise and fall time
performance, improved system noise energy (dynamic)
immunity, optimum device speed for both output switching
low-to-high (tPLH) and output switching high-to-low (tPHL),
and in general the identical high and low DC and AC char-
acteristics normally associated with a good complemen-
tary output drive circuit. MOS system design, simulation,
and performance are significantly enhanced by equal high
and low DC and AC performance ratings and one tight
specification limit for all package styles.
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CD40xxB pdf, datenblatt
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Family Ratings and Specifications‡
Standardized Absolute Maximum Ratings For B-Series CMOS Integrated Circuits
DC Supply Voltage, VDD
Voltage Reference to VSS Terminal. . . . . . . . . . . . . -0.5V to +20V
Input Voltage, All Inputs . . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current,
For Any One Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Lead Temperature (During Soldering)
At Distance 1/16in. ± 1/32in. (1.59mm ± 0.79mm)
from Case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Power Dissipation Per, PD
TA = -55oC to +100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
TA = +100oC to +125oC . . . Derate Linearly at 12mW/oC to 200mW
Device Dissipation Per Output Transistor
For TA = Full Package Temperature Range
(All Package Test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range, TA . . . . . . . . . . . . . -55oC to +125oC
Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . -65oC to +150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Supply, Voltage Range
For TA = Full Package Temperature Range . . . . . . . +3V to +18V
Standardized DC Electrical Specification For B-Series CMOS Integrated Circuits
TEST CONDITIONS
LIMITS
+25oC
PARAMETERS SYMBOL
VO
(V)
VIN VDD
(V) (V) -55oC -40oC +85oC +125oC MIN TYP MAX UNIT
Quiescent Device
IDD Max
-
0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA
Current
-
0, 10
10
0.5 0.5
15
15
- 0.01 0.5 µA
Gates, Inverters
(Note 1)
-
0, 15
15
1 1 30 30
- 0.01 1
µA
-
0, 20
20
5
5 150 150
- 0.02 5
µA
Buffers, Flip-
Flops, Latches,
Multi-Level Gates
(MSI-1 Types)
(Note 1)
-
0, 5 5
1 1 30 30
- 0.02 1
µA
-
0, 10
10
2 2 60 60
- 0.02 2
µA
-
0, 15
15
4
4 120 120
- 0.02 4
µA
-
0, 20
20
20 20 600 600
- 0.04 20 µA
Complex Logic
(MSI-2 Types)
(Note 1)
-
0, 5 5
5
5 150 150
- 0.04 5
µA
-
0, 10
10
10 10 300 300
- 0.04 10 µA
-
0, 15
15
20 20 600 600
- 0.04 20 µA
- 0, 20 20 100 100 3000 3000 - 0.08 100 µA
Output Low (Sink)
Current Min
IOL Min
0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA
0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA
1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA
Output High (Source) IOH Min
4.6
0, 5
5 -6.4 -0.61 -0.42 -0.36 -0.51 -1
- mA
Current, Min
2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA
9.5
0, 10
10
-1.6 -1.5 -1.1
-0.9 -1.3 -2.6
-
mA
13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA
‡ For specific technical information on each individual device type, refer to the appropriate data sheet in Harris AnswerFAX.
See Section 8, “How to use AnswerFAX”, in this selection guide.
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