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AD7792 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7792
Beschreibung (AD7792 / AD7793) 16/24-Bit Sigma-Delta ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 18 Seiten
AD7792 Datasheet, Funktion
www.DataSheet4U.com
Low Power, 16/24-Bit Sigma-Delta ADC with
Low-Noise In-Amp and Embedded Reference
Preliminary Technical Data
AD7792/AD7793
FEATURES
Resolution:
AD7792: 16-Bit
AD7793: 24-Bit
Low Noise Programmable Gain Instrumentation-Amp
RMS noise: 80 nV (Gain = 64)
Bandgap Reference with 5ppm/ C Drift typ
Power
Supply: 2.7 V to 5.25 V operation
Normal: 400 µA typ
Power-down: 1 µA max
Update Rate: 4 Hz to 500 Hz
Simultaneous 50 Hz/60 Hz Rejection
Internal Clock Oscillator
Programmable Current Sources (10 µA/200 µA/1 mA)
On-Chip Bias Voltage Generator
100 nA Burnout Currents
Independent Interface Power Supply
16-Lead TSSOP Package
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Thermocouple Measurements
RTD Measurements
Thermistor Measurements
FUNCTIONAL BLOCK DIAGRAM
GND AVDD
REFIN(+)/AIN3(+) REFIN(-)/AIN3(-)
VBIAS
VDD
AIN1(+)
AIN1(-)
AIN2(+)
AIN2(-)
IOUT1
MUX
VDD
GND
BANDGAP
REFERENCE
GND
IN-AMP
SIGMA DELTA
ADC
INTERNAL
CLOCK
SERIAL
INTERFACE
AND
CONTROL
LOGIC
IOUT2
AD7792/AD7793
CLK
DOUT/RDY
DIN
SCLK
CS
DVDD
Figure 1.
GENERAL DESCRIPTION
The AD7792/AD7793 is a low power, complete analog front end
for low frequency measurement applications. The
AD7792/AD7793 contains a low noise 16/24-bit ∑-∆ ADC with
three differential analog inputs. The on-chip low noise
instrumentation amplifier means that signals of small
amplitude can be interfaced directly to the ADC. With a gain
setting of 64, the rms noise is 80 nV when the update rate equals
16.6 Hz.
The device contains a precision low noise, low drift internal
bandgap reference for absolute measurements. An external
reference can also be used if ratiometric measurements are re-
quired. On-chip programmable excitation current sources can
be used to supply a constant current to RTDs and thermistors
while the 100 nA burnout currents can be used to ensure that
the sensors connected to the ADC are not burnt out. For ther-
mocouple applications, the on-chip bias voltage generator steps
up the common mode voltage from the thermocouple so that it
is within the ADC’s allowable range.
The device can be operated with the internal clock or, alterna-
tively, an external clock can be used if synchronizing several
devices. The output data rate from the part is software pro-
grammable and can be varied from 4 Hz to 500 Hz.
The part operates with a power supply from 2.7 V to 5.25 V. It
consumes a current of 450 uA maximum and is housed in a 16-
lead TSSOP package.
REV.PrF
6/04.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD7792 Datasheet, Funktion
www.DataSheet4U.com
AD7792/AD7793
Preliminary Technical Data
TIMING CHARACTERISTICS4, 5
Table 2. (AVDD = 2.7 V to 5.25 V; DVDD = 2.7 V to 5.25 V; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise
noted.)
Parameter
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK High Pulsewidth
t4
100
ns min
SCLK Low Pulsewidth
Read Operation
t1 0
ns min
CS Falling Edge to DOUT/RDY Active Time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
t26 0
ns min
SCLK Active Edge to Data Valid Delay7
60
ns max
DVDD = 4.75 V to 5.25 V
80
t58, 9
10
ns max
ns min
DVDD = 2.7 V to 3.6 V
Bus Relinquish Time after CS Inactive Edge
80 ns max
t6
100
ns max
SCLK Inactive Edge to CS Inactive Edge
t7
10
ns min
SCLK Inactive Edge to DOUT/RDY High
Write Operation
t8 0
ns min
CS Falling Edge to SCLK Active Edge Setup Time7
t9
30
ns min
Data Valid to SCLK Edge Setup Time
t10 25
ns min
Data Valid to SCLK Edge Hold Time
t11 0
ns min
CS Rising Edge to SCLK Edge Hold Time
4 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
5 See Figure 3 and Figure 4.
6 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
7 SCLK active edge is falling edge of SCLK.
8 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
9 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
REV.PrF 6/04 | Page 6

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AD7792 pdf, datenblatt
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AD7792/AD7793
Preliminary Technical Data
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
CR7
WEN(0)
CR6
R/W(0)
CR5
RS2(0)
CR4
RS1(0)
CR3
RS0(0)
CR2
CREAD(0)
CR1
0(0)
CR0
0(0)
Table 5. Communications Register Bit Designations
Bit Location Bit Name
Description
CR7
WEN
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
CR6 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
CR5–CR3
RS2–RS0
Register Address Bits. These address bits are used to select which of the ADC’s registers are being
selected during this serial interface communication. See Table 6.
CR2
CREAD
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 01011100 must be written to the communications register. To exit the continuous read
mode, the instruction 01011000 must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.
CR1–CR0
0
These bits must be programmed to logic 0 for correct operation.
Table 6. Register Selection
RS2 RS1 RS0
Register
000
Communications Register during a Write Operation
000
Status Register during a Read Operation
001
Mode Register
010
Configuration Register
011
Data Register
100
ID Register
101
IO Register
110
Offset Register
111
Full-Scale Register
Register Size
8-Bit
8-Bit
16-Bit
16-Bit
16 / 24-Bit
8-Bit
8-Bit
16-Bit (AD7792)/24-Bit (AD7793)
16-Bit (AD7792)/24-Bit (AD7793)
REV.PrF 6/04 | Page 12

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