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GS841Z36AT Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS841Z36AT
Beschreibung 4Mb Pipelined and Flow Through Synchronous NBT SRAMs
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS841Z36AT Datasheet, Funktion
www.DataSheet4U.com
GS841Z18/36AT-180/166/150/100
100-Pin TQFP
Commercial Temp
Industrial Temp
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
180 MHz–100 MHz
3.3 V VDD
2.5 V and 3.3 V VDDQ
Features
• 256K x 18 and 128K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
The GS841Z18/36AT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS841Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS841Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Parameter Synopsis
tCycle
tKQ
IDD
tKQ
tCycle
IDD
–180
5.5 ns
3.2 ns
335 mA
8 ns
9.1 ns
210 mA
–166
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
–150
6.6 ns
3.8 ns
280 mA
10 ns
12 ns
165 mA
–100
10 ns
4.5 ns
190 mA
12 ns
15 ns
135 mA
Rev: 1.02 11/2004
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology






GS841Z36AT Datasheet, Funktion
www.DataSheet4U.com
GS841Z18/36AT-180/166/150/100
Synchronous Truth Table
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
R External L-H L L H X L H L L L Q
B
Next L-H L
H XX X X XLL Q
1,10
R External L-H L L H X L H L H L High-Z 2
B
Next L-H L
H X X X X X H L High-Z 1,2,10
W External L-H L
L LL L H LXL D
3
B Next L-H L H X L X X X X L D 1,3,10
B
Next L-H L
H X H X X X X L High-Z 1,2,3,10
D
None L-H L
L X X H X X X L High-Z
D
None L-H L
L X X X X H X L High-Z
D
None L-H L
L X X X L X X L High-Z
D
None L-H L
L L H L H L X L High-Z 1
Deselect Cycle, Continue
D
None L-H L
H X X X X X X L High-Z 1
Sleep Mode
None X X X X X X X X X H High-Z
Clock Edge Ignore, Stall
Current L-H H
X XX X X XXL
-
4
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.02 11/2004
6/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

6 Page









GS841Z36AT pdf, datenblatt
www.DataSheet4U.com
GS841Z18/36AT-180/166/150/100
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
0.5 to 4.6
V
VI/O
Voltage on I/O Pins
0.5 to VDDQ +0.5 (4.6 V max.)
V
VIN
Voltage on Other Input Pins
0.5 to VDD +0.5 (4.6 V max.)
V
IIN Input Current on Any Pin
+/20
mA
IOUT Output Current on Any I/O Pin
+/20
mA
PD Package Power Dissipation
1.5 W
TSTG Storage Temperature
55 to 125
oC
TBIAS
Temperature Under Bias
55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.02 11/2004
12/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

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