|
|
Teilenummer | C1162 |
|
Beschreibung | MSC1162A | |
Hersteller | Oki | |
Logo | ||
Gesamt 14 Seiten E2C0034-27-Y5
www.DataSheet4U.com
¡¡SemicondSucetormiconductor
This version: NMoSvC. 11919672A
Previous version: Jul. 1996
MSC1162A
40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
GENERAL DESCRIPTION
The MSC1162A is a monolithic IC designed for directly driving the grid and anode of the vacuum
fluorescent display tube. The device contains a 40-bit bidirectional shift register, a 40-bit latch
circuit, and 40-output circuit on a single chip.
Display data is serially stored in the shift register at the rising edge of a clock pulse.
Setting the CL pin low allows all the driver outputs to be driven low, which makes it possible to
set the display blanking.
Also, setting both of the CL and CHG pins high allows all the driver outputs to be driven high,
which provides the easy testing of all lights after final assembly of a VFD tube panel.
The MSC1162A is compatible with the MSC1162.
FEATURES
• Logic Supply Voltage (VCC) : 5V
• Driver Supply Voltage (VHV): 65V
• Driver Output Current
IOHVH1 (Only one driver output : "H") : –40mA
IOHVH2 (All the driver outputs : "H") : –2mA
IOHVL:1mA
• Directly connected to VFD tube without pull-down resistors
• Data Transfer Speed: 4MHz
• Package :
60-pin plastic SSOP (SSOP60-P-700-0.65-BK) (Product name : MSC1162AGS-BK)
1/14
www.DataSheet4U.com
¡ Semiconductor
MSC1162A
PIN DESCRIPTION
Symbol
CLK
DIN
DOUT
LS
CL
CHG
VHO1-40
VHV
VCC
GND1
GND2
Type
I
I
O
I
I
I
O
Description
Shift register clock input pin.
Shift register reads data through DIN while the CLK pin is low state and the data in the shift
register is shifted from one stage to the next stage at the rising edge of the clock.
Serial data input pin of the shift register.
Display data (positive logic) is input in through the DIN pin synchronization with clock.
Serial data output pin of the shift register.
Data is output through the DOUT pin in synchronization with the CLK signal.
When R/L = High, the data of PO40 in the shift register is output through the DOUT pin.
When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin.
Latch strobe input pin
When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS
goes from high to low, the parallel output data (PO1-40) of the shift register is held.
Clear input pin with a built-in pull-up resistor
The CL pin is normally being set high.
If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high
irrespective of the states of the latch outputs.
If the CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and latch outputs.
This allows display blanking to be set.
Input for testing (with a pull-down resistor)
The CL pin is normally being set low.
If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase
with the corresponding latch outputs (O1 to O40).
If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low
irrespective of the states of the latch outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the
latch outputs.
This provides the easy testing of all lights after final assembly.
High voltage driver outputs for driving VFD tube
The driver outputs are in phase with the corresponding latch outputs (O1 to O40).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
Power supply pin for driver circuits of VFD tube
Power supply pin for logic
GND pin for driver circuits of a VFD tube. (D-GND)
Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND.
GND pin for the logic circuits. (L-GND)
Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND.
6/14
6 Page www.DataSheet4U.com
¡ Semiconductor
MSC1162A
NOTES ON USE
1. Connect GND1 to GND2 externally to be an equal potential voltage.
2. The contents of the shift register are undefined when the power is applied.
Therefore, unnecessary driver outputs may be driven high just after power-on, and
the VFD tube may flicker.
To avoid this, follow the procedures:
1) Apply the driver power supply after applying the logic power supply, with the
CL pin remained low.
2) Start displaying by setting the CL pin high after in putting display data the shift
register through the DIN pin.
12/14
12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ C1162 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
C1161 | NPN Transistor - 2SC1161 | SavantIC |
C1162 | NPN Transistor - 2SC1162 | Renesas |
C1162 | MSC1162A | Oki |
C1162 | NPN Plastic Encapsulated Transistor | SeCoS |
C1163 | NPN Transistor - 2SC1163 | SavantIC |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |