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D72103A Schematic ( PDF Datasheet ) - NEC

Teilenummer D72103A
Beschreibung UPD72103A
Hersteller NEC
Logo NEC Logo 




Gesamt 70 Seiten
D72103A Datasheet, Funktion
www.DataSheet4U.com
µPD72103A
HDLC CONTROLLER
© 1997
µPD72103A
Document No. S10766EJ9V0UM00 (9th edition)
Date Published March 1997 N CP(N)
Printed in Japan






D72103A Datasheet, Funktion
www.DataSheet4U.com
TABLE OF CONTENTS
CHAPTER 1 GENERAL ............................................................................................................................ 1
1.1 Features ..................................................................................................................................... 1
1.2 Block Diagram .......................................................................................................................... 2
1.3 Internal Block Functions ......................................................................................................... 3
1.4 Pin Configuration (Top View) ................................................................................................. 4
1.5 Pin Functions ........................................................................................................................... 6
1.6 Initialization via Reset ........................................................................................................... 11
CHAPTER 2 BUS INTERFACE ..............................................................................................................13
2.1 Internal Registers ...................................................................................................................13
2.1.1 Control register ............................................................................................................................. 14
2.1.2 Internal status register .................................................................................................................. 15
2.2 DMAC (Direct Memory Access Controller) .........................................................................16
2.2.1 Block transfers .............................................................................................................................. 16
2.2.2 Extension of active (low-level) width of MRD and MWR signals ................................................... 17
2.2.3 Basic timing of DMA ...................................................................................................................... 18
2.2.4 Address/data multiplexing ............................................................................................................. 20
2.3 Interface between µPD72103A and Host Processor ......................................................... 22
2.3.1 Command issuance ...................................................................................................................... 23
2.3.2 Status report ................................................................................................................................. 25
2.3.3 Command chain function .............................................................................................................. 26
2.4 Initialization of External Memory .........................................................................................27
2.5 Methods for Using External Memory .................................................................................. 27
2.5.1 Command table ............................................................................................................................. 27
2.5.2 Status table ................................................................................................................................... 32
2.5.3 Receive buffer address table ........................................................................................................ 36
2.5.4 Receive buffer ............................................................................................................................... 45
2.5.5 Transmit buffer .............................................................................................................................. 45
2.5.6 External memory table configuration example .............................................................................. 45
CHAPTER 3 COMMUNICATION OPERATIONS ...................................................................................47
3.1 Initial Settings ........................................................................................................................47
3.2 Start of Communication Control Operation and Flag Synchronization Setup ............. 48
3.2.1 Transmit operation ........................................................................................................................ 48
3.2.2 Receive operation ......................................................................................................................... 48
3.2.3 Status reporting ............................................................................................................................. 48
3.3 Data Transmission .................................................................................................................49
3.3.1 Transmission timing ...................................................................................................................... 49
3.3.2 Linkage of transmit data ................................................................................................................ 49
3.3.3 Transmit buffer chain .................................................................................................................... 50
3.3.4 Transmission underrun ................................................................................................................. 50
3.4 Data Reception .......................................................................................................................51
3.4.1 Reception timing ........................................................................................................................... 51
3.4.2 Separation of receive data ............................................................................................................ 53
–i–

6 Page









D72103A pdf, datenblatt
www.DataSheet4U.com
CHAPTER 1 GENERAL
1.3 Internal Block Functions
Name
Bus interface
Internal controller
DMAC
(Direct Memory
Access Controller)
Tx FIFO
Rx FIFO
Transmitter
Receiver
Internal buses
Function
Interface between the µPD72103A and external memory or external
host processor
HDLC framing including the DMAC, transmitter, and receiver block
control
Controls transfer of data in external memory to the internal controller
or transmitter, or controls writing of data to external memory from
the internal controller or receiver
A 32-byte buffer for transmitting transmit data from the DMAC to
the transmitter
A 128-byte buffer for transmitting receive data from the receiver
to the DMAC
Converts contents of TX FIFO to HDLC frames that are sent as
serial data
Writes data received in HDLC frames to RX FIFO
These buses, which include a 24-bit address bus and 8/16-bit
data buses, connect the internal controller, DMAC, FIFOs, serial
block, and bus interface block
3

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